Each MPSoC is built using similar architecture. The ZU5 programmable logic (PL) uses four rows of three clock regions. Each clock region contains multiple columns of PL and dedicated block. Each column is composed of a single type of tiles. The number of tiles per column depends on the height of the tile type. A column of configurable logic block (CLB) tiles has 60 tiles. The PCIe® tile is an example of the tallest tile used. A column of PCIe has one tile.
The column width changes based on the tile type for that tile. It is important to understand that the column width for clock regions vertically arranged is constant. In other words, a column of CLB tiles in the blue clock region extends to the same column in the red clock region below it all the way to the last clock region going vertically down so the same width of the column is maintained from clock region to clock region. See Figure 32: FPGA Layout for details.