The clock spine for each clock region is located in the center of each clock region as shown in the following figure. The clocks are distributed vertically using the columns of interconnect tiles which then drive local logic devices in other tiles. Refer to UltraScale Architecture Clocking Resources User Guide (UG572) for more details on the UltraScale clock architecture.
Figure 1. Clock Spine Location
Interconnect tiles are used to route connections between logic tiles. These interconnect tiles are the equivalent to route channels in ASIC designs, and also provide a convenient method to isolate logic regions.