The is where the design may be captured in the AMD Vivado™ Design Suite. As shown in Figure 1, instead of using the IP integrator, Verilog, or VHDL code can also be used for creating the isolated modules. After the design is captured, a functional hierarchy is established, based on your isolation strategy with respect to how data is flowing in your design. These create the logical boundaries which will define the physical isolation as the design flow is implemented. This step is critical as all other activities are based on this hierarchy.
The isolated modules require an additional wrapper after the hierarchy gets established. These modules are captured via an IP integrator. This additional wrapper is required to enable port splitting that might not be allowed by tool generated items, such as the hierarchy created by the triple modular redundancy (TMR) management tool. See Isolation Design Example for Zynq Ultrascale+ MPSoC Application Note (XAPP1336) for further details.
