It is important to include enough required programmable unit (PU) resources in a Pblock to support the assigned module. This is verified by reviewing the resources table when the Pblock is drawn. A Pblock can be of any shape; the shape is defined by the combination of PUs that are assigned to it.
The following table lists out the minimum fence size in terms of PU for the user tiles. For more details on Fence, refer to Isolation Fence.
| Tile | User Tile Description | Fence Size |
|---|---|---|
| SLICEL (CLBL) | Configurable Logic Block. The key logic unit of an FPGA. | Vertical: 1 PU Horizontal: 1 PU |
| SLICEM (CLBM) | Configurable Logic Block. The key logic unit of an FPGA. | Vertical: 1 PU Horizontal: 1 PU |
| DSP |
Digital Signal Processor. A programmable math function (DSP tile is two DSP48E1 slices; analysis was done on DSP48E1 slice; AMD Vivado™ tools only allow selection of a DSP tile). |
Vertical: 1 PU Horizontal: 1 PU |
| BRAM | Block RAM. User-accessible high speed RAM (BRAM tile is RAMB36 which is two RAMB18 blocks; Vivado tools only allow selection of a BRAM tile). | Vertical: 1 PU Horizontal: 1 PU |
| URAM | High density block RAM. User-accessible high speed RAM | Vertical: 1 PU Horizontal: 1 PU |
| HDIO | General purpose I/O block | Vertical: 1/2 PU (12 IO) Horizontal: 1/2 PU (12 IO) |
| HPIO | High Performance I/O block | Vertical: 1 PU (52 IO) Horizontal: 1 PU (52 IO) |
| GTX/GTY QUAD | High speed transceiver. The GTX or GTY Quad tile is made up of four channels. PR Units in different Pblocks are allowed to abut as long as one channel along the abutment is not used. | Vertical: 1 PU Horizontal: 1 PU PU GTX/Y Channel |
| PCI-E | PCI Express® Endpoint Block | Vertical: 1 PU Horizontal: 1 PU |
| SYSMON | System Monitor. Contains analog-to-digital converters (ACDs). | Vertical: 1 PU Horizontal: 1 PU |
| CMAC | Centralized Media Access Control Block | Vertical: 1 PU Horizontal: 1 PU |
| INTERLAKEN | High Speed Chip to Chip pack transfer port | Vertical: 1 PU Horizontal: 1 PU |
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