Conclusion

Isolation Design Flow for Zynq UltraScale+ MPSoCs and UltraScale+ FPGAs (XAPP1335)

Document ID
XAPP1335
Release Date
2023-05-15
Revision
2.2 English

The focus of this document is to help design engineering professionals understand the new features and limitations of implementing the AMD Isolation Design Flow (IDF) technology with AMD Zynq™ UltraScale+™ MPSoC programmable logic (PL) and AMD UltraScale+™ architecture. It helps implement the IDF technology as part of your overall layers of protection strategy used in functional safety and security design architectures. Although the impact of using IDF is not discussed in this document, you are encouraged to discuss such solutions with your AMD Field Application Engineer or other AMD resources. This document also discusses about IDF+DFX design flow. The Isolation Design Flow (IDF) and Dynamic Function eXchange (DFX) are two production solutions from AMD.