Trusted Routing Rules

Isolation Design Flow for Zynq UltraScale+ MPSoCs and UltraScale+ FPGAs (XAPP1335)

Document ID
XAPP1335
Release Date
2023-05-15
Revision
2.2 English

Trusted routing is automatic when HD.ISOLATED is set on the isolated modules of a design. The design tools recognize the communication between isolated Pblocks and use the trusted routing resources. Thus, the tools do everything automatically for you. However, some rules must be adhered to if safe communication between isolated modules is to be guaranteed. The rules outlined in this section are a general guideline that the isolation designers must know with regards to the isolation routing concepts.

Note: The Vivado tools automatically follow each of the rules listed below. As a good design practice, it is recommended to understand these IDF rules and take the suggested precautions to avoid violating them, even though Vivado tools takes the necessary steps to ensure that they are followed. The changes done by the tools to incorporate trusted routing rules appear in the netlist after the synthesis phase.

Following are the rules listed for trusted routing:

Rule 1: Feed-through signals are not allowed without buffering of some kind such as LUT or FF.

  • If a signal is directly connected to both an input port and an output port, it must be buffered
  • Direct instantiation of a buffer (LUT1, for example) is recommended. This isolates the wire segments in each of the isolated Pblocks with the LUT buffer, preventing a common (shorted) net throughout both regions

Problem: The following figure shows IDF rules violation because of the short between two isolated Pblocks.

Figure 1. Short created by Feed-Trough Signal

Solution: Feed-through signals need to be buffered. This can be achieved either through HDL coding to ensure that there is some unique driver on the output port, by direct instantiation of a LUT, or flip-flop buffer as shown in the following figure, or by letting the Vivado tools address the issue using separate wire segments.

Figure 2. Elimination of Short by Instantiation of a LUT Buffer

Rule 2: An isolated module’s output port (driver) cannot connect to more than one isolated module’s input port (load). Stated differently, port-to-port connections must be singular:

  • Two different ports need to be created for such a connection.
  • Each port must not violate Rule 3

Problem: In the following figure, the orange and blue colored nets creates a potential connection between Isolated Module 2 and Isolated Module 3 which was never intended in the original design, and hence violates isolation between Isolated Modules 2 and 3.

Figure 3. Multi-Port Connection Causing Connectivity between Isolated Module 2 and Isolated Module 3

Solution: You must create multiple output ports as many as needed to drive multiple input ports of other isolated modules as shown in the following figure, or you can let the Vivado tools split the offending ports. If you choose to let Vivado do this for you, the HDL does not need to be modified to achieve this. The tools split the ports at the netlist level.

Figure 4. Elimination of Unintended Connection Using Multiple Output Ports

Rule 3: One signal cannot drive two different output ports of the same function:

  • Each port must have a unique driver.
  • Direct instantiation of a buffer (LUT1, for example) is necessary. This isolates regions with the LUT preventing a shorted net.
Problem: In the following figure, even though there are separate output ports on Isolated Module 1 going to two different isolated modules – 2 and 3, inside Isolated Module 1 it is the same orange or blue net going to two different isolated modules. Thus, Isolated Module 2 and 3 might get connected via the orange or blue nets.
Figure 5. Unintended Connectivity between Isolated Module 2 and Isolated Module 3 Inside Isolated Module 1

Another variant of this problem can be when driver of an isolated module drives itself as well as another isolated module as shown in the following figure. This also violates the IDF rules for Trusted Routing.

Figure 6. Unintended Connectivity between Isolated Module 1 and Isolated Module 2

Solution: Each port driver needs to be buffered. This can be achieved through HDL coding to ensure that there is some unique driver for each output port, by direct instantiation of a LUT buffer or flip-flip as shown below in the following figures, or by letting the Vivado tools address the issue using separate wire segments.

Figure 7. Elimination of Unintended Connectivity Using LUT Buffers
Figure 8. Elimination of Unintended Connectivity Using LUT Buffers

The developer can manually modify the HDL to meet the IDF rules and manually split the nets, as well as add LUTs as described below. Additionally, this automatic modification by Vivado tools can be disabled by setting the parameter HD.ISOLATED_DISABLE_NETSPLIT to 1 using the following syntax:
set_parameter HD.ISOLATED_DISABLE_NETSPLIT 1

However, it is highly recommended that you let the tools take care of the trusted routing.