Isolated designs must keep the amount of top level logic to a minimum. In a typical Isolation Design Flow (IDF) design, the only logic at the top level should be clock logic. Any component that is not part of an isolated module in the design hierarchy is optimized to the top level. Because isolation is defined by the HD.ISOLATED attribute being set on a hierarchical module, all top logic is, by default, not isolated. This has the following implications:
- There are no placement constraints on top level logic other than
it will not be placed in the fence.
- Top level logic can be placed in any isolated Pblock.
- There are no routing restrictions on top level logic other than
it will not violate the fence with used programmable interconnect points
(PIPs).
- Top level routes can route to, from, and through any isolated Pblock.
Important: Vivado tools automatically take care of the
placement of top logic. It ensures that top level logic is not placed in the fence.
If there is a large empty space in a design that is not encompassed by any Pblock,
Vivado might place top logic in that empty space.