The Vivado Isolation Verifier (VIV) verifies that an FPGA design partitioned into isolated Pblocks meets stringent standards for fail-safe design. VIV is a collection of six design rule checks (DRCs) intended to aid FPGA developers in producing and documenting fault-tolerant FPGA applications developed with the AMD Isolation Design Flow (IDF). Historically, VIV (VIV1) was a Tcl script that ran in the Vivado tool framework in the form of user defined DRCs. As part of adding support of IDF for UltraScale+ architecture, AMD has released VIV2 which has the same set of six DRCs, but they are now are a part of Vivado built-in system DRCs. For convenience, in this application note VIV2 will be referred to as VIV.
Vivado Isolation Verifier (VIV) 2.0 is
available from the AMD Vivado™ Design Suite 2018.3. Prior
to Vivado version 2021.1, users needed to enable
VIV by setting a parameter hd.enableIDFDRC to True. But from Vivado version 2021.1
onwards, VIV gets enabled automatically when the
tool detects HD.ISOLATED property is set to True. Refer to
Vivado Isolation Verifier User Guide (UG1291) for more detailed
information on VIV2.
- To run this tool, open the Report DRC window in the Reports
drop-down menu as shown in the following figure.
- In the Rules window, under Isolation, select Provenance and Constraints, and click OK.
The result displays in the DRC window as shown in the following figure.
Ensure there are no errors in the DRC report and then run Implementation.