Boundary of Clock Regions

Isolation Design Flow for Zynq UltraScale+ MPSoCs and UltraScale+ FPGAs (XAPP1335)

Document ID
XAPP1335
Release Date
2023-05-15
Revision
2.2 English

Gaps can be seen at the boundary of the clock regions. These are not valid fences and do not provide any isolation. The following figure shows such a gap as that is seen in Vivado GUI.

Figure 1. Gap between Two Clock Regions Highlighted in White Rectangle That Looks like a Fence, but It Is Not