When this signal is positive, it indicates that the error detection logic has
identified mismatches between the expected and received value of CRC32 in the received
packet. When a CRC32 error is detected, the received packet is marked as containing an
error and is sent with rx_errout asserted during the last transfer (the
cycle with rx_eopout asserted), unless
ctl_rx_ignore_fcs is asserted. This signal is asserted for one
clock period for each CRC32 error detected.