Pause Interface - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID

PG210

Release Date

2024-06-07

Version

4.1 English

The following tables show the Pause interface I/O ports.

Table 1. Pause Interface - Control Ports
Name	I/O	Clock Domain	Description
ctl_rx_pause_enable[8:0]	I	clk	RX pause enable signal. This input is used to enable the processing of the pause quanta for the corresponding priority. Note: This signal only affects the RX user interface and not the pause processing logic
ctl_tx_pause_enable[8:0]	I	clk	TX pause enable signal. This input is used to enable the processing of the pause quanta for the corresponding priority. This signal gates transmission of pause packets.

Table 2. Pause Interface - TX Path
Name	I/O	Clock Domain	Description
ctl_tx_pause_req[8:0]	I	clk	If a bit of this bus is set to 1, the core transmits a pause packet using the associated quanta value on the ctl_tx_pause_quanta[8:0][15:0] bus. If bit[8] is set to 1, a global pause packet is transmitted. All other bits cause a priority pause packet to be transmitted.
ctl_tx_resend_pause	I	clk	Retransmit pending pause packets. When this input is sampled as 1, all pending pause packets are retransmitted as soon as possible (that is, after the current packet in flight is completed) and the retransmit counters are reset. This input should be pulsed to 1 for one cycle at a time.
ctl_tx_pause_quanta[8:0][15:0]	I	clk	These nine buses indicate the quanta to be transmitted for each of the eight priorities in priority based and global pause operations. The value for ctl_tx_pause_quanta[8] is used for global pause operation. All other values are used for priority based pause operation.
ctl_tx_pause_refresh_timer[8:0][15:0]	I	clk	These nine buses set the retransmission time of pause packets for each of the eight priorities in priority based pause operation and the global pause operation. The values for ctl_tx_pause_refresh_timer[8] is used for global pause operation. All other values are used for priority pause operation.
ctl_tx_da_gpp[47:0]	I	clk	Destination address for transmitting global pause packets.
ctl_tx_sa_gpp[47:0]	I	clk	Source address for transmitting global pause packets.
ctl_tx_ethertype_gpp[15:0]	I	clk	Ethertype for transmitting global pause packets.
ctl_tx_opcode_gpp[15:0]	I	clk	Opcode for transmitting global pause packets.
ctl_tx_da_ppp[47:0]	I	clk	Destination address for transmitting priority pause packets.
ctl_tx_sa_ppp[47:0]	I	clk	Source address for transmitting priority pause packets.
ctl_tx_ethertype_ppp[15:0]	I	clk	Ethertype for transmitting priority pause packets.
ctl_tx_opcode_ppp[15:0]	I	clk	Opcode for transmitting priority pause packets.
stat_tx_pause_valid[8:0]	O	clk	If a bit of this bus is set to 1, the core has transmitted a pause packets. If bit [8] is set to 1, a global pause packet is transmitted. All other bits cause a priority pause packet to be transmitted.

Table 3. Pause Interface - RX
Name	I/O	Clock Domain	Description
ctl_rx_pause_ack[8:0]	I	clk	Pause acknowledge signal. This bus is used to acknowledge the receipt of the pause frame from the user logic.
ctl_rx_check_ack	I	clk	Wait for acknowledge. IF this input is set to 1, the core uses the ctl_rx_pause_ack[8:0] bus for pause processing. If this input is set to 0, ctl_rx_pause_ack[8:0] is not used.
ctl_rx_enable_gcp	I	clk	A value of 1 enables global control packet processing.
ctl_rx_check_mcast_gcp	I	clk	A value of 1 enables global control multicast destination address processing.
ctl_rx_check_ucast_gcp	I	clk	A value of 1 enables global control unicast destination address processing.
ctl_rx_pause_da_ucast[47:0]	I	clk	Unicast destination address for pause processing.
ctl_rx_check_sa_gcp	I	clk	A value of 1 enables global control source address processing.
ctl_rx_pause_sa[47:0]	I	clk	Source address for pause processing.
ctl_rx_check_etype_gcp	I	clk	A value of 1 enables global control ethertype processing.
ctl_rx_etype_gcp[15:0]	I	clk	Ethertype field for global control processing
ctl_rx_check_opcode_gcp	I	clk	A value of 1 enables global control opcode processing.
ctl_rx_opcode_min_gcp[15:0]	I	clk	Minimum global control opcode value
ctl_rx_opcode_max_gcp[15:0]	I	clk	Maximum global control opcode value
ctl_rx_enable_pcp	I	clk	A value of 1 enables priority control packet processing
ctl_rx_check_mcast_pcp	I	clk	A value of 1 enables priority control multicast destination address processing
ctl_rx_check_ucast_pcp	I	clk	A value of 1 enables priority control unicast destination address processing
ctl_rx_pause_da_mcast[47:0]	I	clk	Multicast destination address for pause processing.
ctl_rx_check_sa_pcp	I	clk	A value of 1 enables priority control source address processing
ctl_rx_check_etype_pcp	I	clk	A value of 1 enables priority control ethertype processing
ctl_rx_etype_pcp[15:0]	I	clk	Ethertype field for priority control processing
ctl_rx_check_opcode_pcp	I	clk	A value of 1 enables priority control opcode processing
ctl_rx_opcode_min_pcp[15:0]	I	clk	Minimum priority control opcode value
ctl_rx_opcode_max_pcp[15:0]	I	clk	Maximum priority control opcode value
ctl_rx_enable_gpp	I	clk	A value of 1 enables global pause packet processing
ctl_rx_check_mcast_gpp	I	clk	A value of 1 enables global pause multicast destination address processing
ctl_rx_check_ucast_gpp	I	clk	A value of 1 enables global pause unicast destination address processing
ctl_rx_check_sa_gpp	I	clk	A value of 1 enables global pause source address processing.
ctl_rx_check_etype_gpp	I	clk	A value of 1 enables global pause ethertype processing
ctl_rx_etype_gpp[15:0]	I	clk	Ethertype field for global pause processing
ctl_rx_check_opcode_gpp	I	clk	A value of 1 enables global pause opcode processing.
ctl_rx_opcode_gpp[15:0]	I	clk	Global pause opcode value.
ctl_rx_enable_ppp	I	clk	A value of 1 enables priority pause packet processing
ctl_rx_check_mcast_ppp	I	clk	A value of 1 enables priority pause multicast destination address processing
ctl_rx_check_ucast_ppp	I	clk	A value of 1 enables priority pause unicast destination address processing
ctl_rx_check_sa_ppp	I	clk	A value of 1 enables priority pause source address processing
ctl_rx_check_etype_ppp	I	clk	A value of 1 enables priority pause ethertype processing
ctl_rx_etype_ppp[15:0]	I	clk	Ethertype field for priority pause processing
ctl_rx_check_opcode_ppp	I	clk	A value of 1 enables priority pause opcode processing
ctl_rx_opcode_ppp[15:0]	I	clk	Priority pause opcode value
ctl_rx_forward_control	I	clk	A value of 1 indicates that the core forwards control packets. A value of 0 causes core to drop control packets.
stat_rx_pause_valid [8:0]	O	clk	Indicates that a pause packet was received and the associated quanta on the stat_rx_pause_quanta[8:0][15:0] bus is valid and must be used for pause processing. If an 802.3x MAC Pause packet is received, bit [8] is set to 1.
stat_rx_pause_quanta[8:0] [15:0]	O	clk	These nine buses indicate the quanta received for each of the eight priorities in priority based pause operation and global pause operation. If an 802.3x MAC Pause packet is received, the quanta is placed in value[8].
stat_rx_pause_req [8:0]	O	clk	Pause request signal. When the RX receives a valid pause frame, it sets the corresponding bit of this bus to 1 and keep it at 1 until the pause packet has been processed.