Table 1. CONFIGURATION_RX_FLOW_CONTROL_REG2: 0098
Bits |
Default |
Type |
Signal |
0 |
0 |
RW |
ctl_rx_check_mcast_gcp |
1 |
0 |
RW |
ctl_rx_check_ucast_gcp |
2 |
0 |
RW |
ctl_rx_check_sa_gcp |
3 |
0 |
RW |
ctl_rx_check_etype_gcp |
4 |
0 |
RW |
ctl_rx_check_opcode_gcp |
5 |
0 |
RW |
ctl_rx_check_mcast_pcp |
6 |
0 |
RW |
ctl_rx_check_ucast_pcp |
7 |
0 |
RW |
ctl_rx_check_sa_pcp |
8 |
0 |
RW |
ctl_rx_check_etype_pcp |
9 |
0 |
RW |
ctl_rx_check_opcode_pcp |
10 |
0 |
RW |
ctl_rx_check_mcast_gpp |
11 |
0 |
RW |
ctl_rx_check_ucast_gpp |
12 |
0 |
RW |
ctl_rx_check_sa_gpp |
13 |
0 |
RW |
ctl_rx_check_etype_gpp |
14 |
0 |
RW |
ctl_rx_check_opcode_gpp |
15 |
0 |
RW |
ctl_rx_check_mcast_ppp |
16 |
0 |
RW |
ctl_rx_check_ucast_ppp |
17 |
0 |
RW |
ctl_rx_check_sa_ppp |
18 |
0 |
RW |
ctl_rx_check_etype_ppp |
19 |
0 |
RW |
ctl_rx_check_opcode_ppp |