Revision History - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID
Release Date
4.1 English

The following table shows the revision history for this document.

Section Revision Summary
11/10/2023 Version 4.1
Customizing and Generating the Subsystem Updated images in the section.
Software Driver Initialization Updated the steps to configure timer syncer IP.
General Updates Entire Document
05/10/2023 Version 4.1
Configuration Tab Block RAM Support is added for Statistics Resource Type Option.
10/19/2022 Version 4.1
Port Timer Registers

Added support for Hybrid timer module by providing CORE_CONFIGURATION and RESYNC_CLK_PERIOD values.

05/13/2022 Version 4.1
Resets Added Versal device reset figure.
Ingress Updated 1588 timestamp accuracy information.
Product Specification Add note for PTP timestamp support.
Configuration Registers for 10G/25G Ethernet Subsystem Renamed reg 0154 as GT_WIZ_CONTROL_REG.
Common Clock/Reset Signals Added new ports.
GT_WIZ_CONTROL_REG: 0154 Add bits 3 to 22.
10/27/2021 Version 4.0
General updates Updated for AMD Versal™ GTM support.
Simulation Speed Up Added new simulators.
RX Path Control/Status/Statistics Signals Updated the table.
MODE_REG: 0008 Updated the table.
08/02/2021 Version 4.0
Timer Register Map

Port Timer Registers

Added new registers.
GT Selection and Configuration Tab Added new GUI option, Enable GT Interface for Board Based Design.
IEEE 1588 TX/RX Interface Control/Status/Statistics Signals Added ports tx_period_ns and rx_period_ns.
12/16/2020 Version 3.3
PTP 1588 Timer Syncer Block Added in the Example Design.
Customizing and Generating the Subsystem Figures updated
LogiCORE Example Design Clocking and Resets Detailed Diagram of Single Core (Versal) updated
Designing with the Subsystem Port Descriptions
09/01/2020 Version 3.2
N/A Updated for Versal Adaptive SoC support
07/14/2020 Version 3.2
N/A Minor formatting change.
06/03/2020 Version 3.2
RESET_REG: 0004 Add bit 28
MODE_REG: 0008 Add bits 0,1
STAT_RX_STATUS_REG1: 0404 Add bit 0
STAT_GT_WIZ_REG: 04A0 New register
LogiCORE Example Design Clocking and Resets Graphics updated
Board Testing Steps for Auto-Negotiation and Link Training Using AXI4-Lite Interface Clarified steps
Customizing and Generating the Subsystem Vivado IDE updated
Simulation Speed Up Add RS-FEC Enabled Configuration Simulation
Transceiver Core and Status Debug Ports gt_ch_* changed to gt_*
Debugging Auto-Negotiation and Link Training Debugging topics added
10/30/2019 Version 3.1
General Updates Added PCS/PMA 32-bit clocking.

Added ANLT board testing steps when AXI4-Lite enabled.

05/22/2019 Version 3.0
General Updates

Added AXI-4 Statistics counter enablement support.

Added GT Rx receiver option.

12/05/2018 Version 2.5
General Updates

Updated license table for the TSN feature.

Updated description for ctl_rx_min_pakcet_length.

Added a note for runtime switching configuration.

06/06/2018 Version 2.4
General Updates Updated 10G TSN license key information.

Added stat_reg_compare port in the Example Design chapter.

Renamed MAC+PCS/PMA 32-bit 1588 register.

Added table note for Table 3-4.

04/04/2018 Version 2.4
General Updates

Added fee-based Time Sensitive Networking (TSN) feature to Features section in IP Facts.

Added 25G/10G Ethernet MAC+PCS/PMA description to Table 1-2.

Added support for 802.1cm preemption feature to the 25G Supported Features and 10G Supported Features sections in Chapter 1.

Updated the licensing information in Chapter 1.

Added a note to the ctl_local_loopback description in Table 2-12.

Added a note for the ctl_autoneg_bypass signal in Table 2-96.

Added Bit 7 for stat_tx_bad_parity signal in Table 2-110.

Added a note for Bit 1, runtime_switchable signal, in Table 2-128

Added option about 1588 time stamp accuracy in the Ingress section in Chapter 3.

Added the new sections, Ethernet Data Path Parity, and 802.1cm Preemption Feature to Chapter 3.

Updated description in the second paragraph of the Ethernet Data Path Parity second in Chapter 3.

Updated Figures 4-1, 4-2, 4-3, and 4-4

Added Enable Preemption 802.3br option to Table 4-1.

Added the Enable Datapath Parity and Enable Packet Assembly FIFO options to Table 4-2.

Updated a note about default frequencies in Table 3-1.

Added new content to the Required Restraints section in Chapter 4.

Added the .h Header File subsection to the AXI4-Lite Interface Implementation section in Chapter 5.

Updated Figure 6-1 in Chapter 6.

Added Vivado Design Suite User Guide: Using Constraints (UG903) to the References section in Appendix C.

For register and port additions see Changes from v2.3 to v2.4 in Appendix A.

12/20/2017 Version 2.3
General updates

Updated Clause 108 RS-FEC to support the following entries in Table 1-1: Runtime switchable 10G/25G MAC+PCS and Runtime switchable 10/25G PCS-only.

In Table 3-1, changed the name of the first column from "Local Fault Indication" to “Name”.

For port and register additions, removal, and changes, see Changes from v2.3 (10/04/2017) to v2.3 (12/20/2017) in Appendix A.

Updated Figure 3-2.

Added 312.5 MHz for 32-bit 10G to refclk_p0, refclk_n0, tx_serdes_refclk description.

Added a note to the following signals about an invalid preamble: stat_rx_bad_sfd, stat_rx_bad_preamble, stat_rx_bad_preamble_*, and stat_rx_bad_sfd_* in tables 2-13, 2-37, and 5-2.

10/04/2017 Version 2.3
General Updates

Added a note to Table 1-1 about auto-negotiation.

Added text about client data logic to the Back-to-Back Continuous Transfers section in Chapter 2.

Removed Table 3-2 and supporting text from the Performance section in Chapter 3.

Added a note about the readable STAT_*_MSB/LSB registers to the Statistics Counters section in Chapter 2.

Added Clock Domain columns to Table 2-4 and Table 2-7 and updated clock domain values in Table 2-11.

Added text about runtime switch mode to beginning of Status Registers section in Chapter 2.

Modified ordinary and transparent clock numbers in Egress section in Chapter 3.

Added text about 2-step 1588 operation for tx_ptp_tstamp_out[80-1:0] and rx_ptp_tstamp_out[80-1:0] in Table 3-1.

Updated Legal Notices and Automotive Applications Disclaimer.

Updated screen captures in Chapter 4.

Added text about SIM_SPEED_UP to the Simulation Speed Up section in Chapter 4.

For axi_ctl_core_mode_switch_* in Table 5-2. changed value to 0x0138

Added, changed and removed some ports and registers. See Changes from v2.2 to v2.3.

06/07/2017 Version 2.2
Introduction and Overview

Updated the Ordering Information section.

Updated the Supported User Interfaces row and the Supported S/W Driver row in the IP Facts table.

See Changes from v2.1 to v2.2 for new variants, feature updates, and port additions and updates.

Updated Table 1-1, Table 1-2, and Table 2-1.

Updated screen captures in Chapter 4.

Removed the AN/LT Clock option from Table 4-1.

04/05/2017 Version 2.1

Changed Supported User Interface in IP Facts table to AXI4-Stream.

Updated feature list with the new features.

Added 10G/25G Runtime Switchable IP Features section and Feature Compatibility Matrix table to Chapter 1.

Added Ordering Information section to Licensing and Ordering Information Chapter 1. Added new license key for standalone 64-bit MAC in new Table 1-2.

Changed Figure 2-1 title to 25 Gbps Core Block Diagram.

Added new Figure 2-2: 10 Gbps Core Block Diagram and Figure 2-4: 64-bit Standalone Version of the MAC for 10 Gbps Operation.

Added AXI4-Stream Interface heading with new 32-bit information throughout the subsections and new timing diagrams for 32-bit operation.

Added new section for the 64-bit 10G MAC offering.

Updated the 64-bit MAC+PCS variant to include the new 32-bit low latency 10G MAC + PCS variant.

Changed "Port Descriptions" name to "Port Descriptions – MAC+PCS Variant"

Added Port Descriptions – 10G Ethernet MAC (64-bit) Variant section and its subsections.

Added new row to Table 2-5 for latency.

Updated most of the Notes in Table 2-39 through Table 2-41.

Added Low Latency 32-bit 10 Gbps MAC with PCS and 10G MAC-only Clocking sections in Chapter 3.

Updated IBUFDS_GTE3 in Figures 3-7 and 3-8.

Removed Figure 3-6 and Figure 3-8 (Synchronous Clock Modes)

Updated the Select Core and Clocking options in Table 4-1.

Updated Figure 4-1 through Figure 4-4.

Replaced “Ethernet MAC+PCS/PMA” with “Ethernet MAC+PCS/PMA-32/64-bit” in all instances and insert "or Ethernet MAC" throughout Table 5-2.

Updated Migration Guide to include the AXI4-Stream Interface

Changed LGMII to XGMII/25GMII throughout.

Changed XXVGMII to 25GMII throughout

For port and register changes, see Appendix A, Migrating and Updating.

11/30/2016 Version 2.0
Overview and Design Flow Steps

Modified “tx_reset and rx_reset” to “s_axi_aresetn' and “active-High” to “active-Low” in the Configuration Register Map section in Chapter 2.

Added text about clearing status registers to the first paragraph of the Status Register Map section in Chapter 2.

Added text about clearing statistics counters to the first paragraph of the Statistics Counters section in Chapter 2.

Updated table notes 3 and 4 and added table note 5 for Table 4-1, Configuration Options.

Added Note about Auto-Negotiation/Link training to the Overview section in Chapter 5.

Added many ports and deleted many ports in Table 5-2, Core xci Top Level Port List. See the Migrating and Updating appendix.

Removed the text “GT Selection and” throughout the Descriptions in Table 2, Core xci Top Level Port List.

10/05/2016 Version 2.0
Product Specification and Design Flow Steps

Added migration from legacy 10G EMAC to Appendix A Migrating and Updating.

Added references to tick_reg_mode_sel throughout.

Updated the following figures: 3-6, 3-7, 3-8, 3-9, 4-1, 4-2, 4-3, 4-4

Updated the description of tx_ptp_1588op_in[1:0] and rx_ptp_tstamp_out[80-1:0] in Table 3-1.

Added support for one-step operation.

Updated several of the port descriptions in Table 3-3.

Added Ethernet MAC value to Select Core option in Table 4-1.

Replaced Include FEC Logic option with Clause 74 (BASE-KR FEC) in Table 4-1.

Added Clause 108 (RS-FEC) option to Table 4-1.

Added the new subsection Simulation Speed Up to the Simulation section in Chapter 4.

Updated the description of ctl_rx_rate_10g_25gn_* in Table 5-2.

Added the rx_ptp_tstamp_valid_out_* to Table 5-2.

Added several new subsection under the AXI4-Lite Interface Implementation section in Chapter 5.

Added Step 5 in the Slow Simulation section in the Debugging appendix.

Added a new paragraph about GTRXRESET in the Clocking and Resets section in the Debugging appendix.

Added the Core xci Top Level Port List section to Chapter 5.

Updated IEEE references to 2015 instead of 2012.

06/08/2016 Version 1.3
Product Specification and Designing with the Subsystem

Changed 10 Gbps to 10.3125 Gbps throughout

Updated Figures 2-2, 3-16, 4-1, 4-2, 4-3,4-4, 5-1, 5-2, 5-3, 5-4, 5-5

Added XGMII to XVGMII throughout.

Changed XXVMII to XVGMII throughout.

Added notes for addresses that support MAC+PCS throughout.

Added Hex Addresses and links in Table 2-24.

Added Bits to Tables 2-25, 2-28, 2-86


Removed General Design Guidelines section in Chapter 3.

Added tx_ptp_rxtstamp_in to Table 3-1

Changed “HSEC” to “10G/25G High Speed Ethernet Subsystem” throughout.

Added Control and Statistics Interface section to Table 4-1

Added GT Location section to Table 4-3 and updated options in the Others section

06/08/2016 Version 1.3
Designing with the Subsystem and Design Flow Steps

Updated some descriptions in Table 4-3, GT Clock Options

Updated Overview in the Chapter 5, Example Design

Updated the descriptions of the optional modules.

Added the Example Design Hierarchy (GT in example design), Runtime Switchable, and IEEE Clause 108 (RS-FEC) Integration sections to Chapter 5.

Completely revised the Shared Logic Implementation section. in Chapter 5.

Added descriptions of the modules that are part of the shared logic wrapper.

Completely revised the Simulation Debug section in Appendix B, Debugging.

Changed 802.3-2012 to 802.3-2015 throughout.

Added one-step operation throughout.

Updated several port descriptions in Table 3-3.

Added Simulation Speed Up section to Chapter 4.

Added new port rx_ptp_tstamp_valid_out_* to Table 5-2.

Added Step 5 to the Slow Simulation section in the Debugging appendix.

Added a paragraph about GTRXRESET to the Clocking and Resets section the Debugging appendix.

04/06/2016 Version 1.2
Product Specification

Added UltraScale+ support.

Added new section that has RSFEC, 1588 1-step and 2-step support.

Added new IEEE 1588 Timestamping section.

Added rx_preambleout [55:0] for both AXI4-Stream interfaces.

Added tx_preamblein [55:0] for AXI4-Stream interface.

Added registers to the Configuration, Status, and Counter register maps.

Changed custom preamble from in-band to out-of-band.

Added text about pm_tick and TIC_REG to Statistics Counter section

Changed polarity of the tx_axis_tuser and rx_axis_tuser signals.

Updated Figure 3-13 and Figure 3-14.

Removed VLane Adjust Mode from Table 4-2.

Removed LBUS material.

Added ctl_tx_ipg_value[3:0] to Table C-4.

12/02/2015 Version 1.1
Performance and Resource Utilization Updated the performance and resource utilization data link.
11/18/2015 Version 1.1
Port Descriptions – MAC+PCS Variant

Added a link to the performance and resource utilization data on the web.

Added the stat_rx_valid_ctrl_code, ctl_tx_custom_preamble_enable, and ctl_rx_custom_preamble_enable signal.

Updated the tx_axis_ tuser signal description.

Updated the Normal Transmission and Aborting a Transmission information in the Transmit AXI4-Stream Interface section.

Added Vivado IDE option details in Design Flow Steps chapter.

Added new information in Example Design chapter.

09/30/2015 Version 1.0
General updates Initial release.