Port Descriptions – PCS Variant - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)
Document ID
PG210
Release Date
2024-06-07
Version
4.1 English

This section shows the 10G/25G PCS core ports. These are the ports when the PCS-only option is provided. There are no FCS functions. The PCS does not contain the Pause and Flow Control ports. The system interface is XGMII/25GMII. The following table shows the PCS variant I/O ports.

Table 1. PCS Variant I/O Ports
Name I/O Clock Domain Description
stat_tx_local_fault O tx_mii_clk A value of 1 indicates the transmit encoder state machine is in the TX_INIT state. This output is level sensitive.
ctl_rx_prbs31_test_pattern_enable I rx_clk_out Corresponds to MDIO register bit 3.42.5 as defined in Clause 45. Takes first precedence.
ctl_rx_test_pattern_enable I rx_clk_out

Test pattern enable for the RX core. A value of 1 enables test mode.

Corresponds to MDIO register bit 3.42.2 as defined in Clause 45. Takes second precedence.
ctl_rx_data_pattern_select I rx_clk_out Corresponds to MDIO register bit 3.42.0 as defined in Clause 45.
ctl_rx_test_pattern I rx_clk_out Test pattern enable for the RX core to receive scrambled idle pattern. Takes third precedence.
ctl_tx_prbs31_test_pattern_enable I tx_mii_clk Corresponds to MDIO register bit 3.42.4 as defined in Clause 45. Takes first precedence.
ctl_tx_test_pattern_enable I tx_mii_clk

Test pattern generation enable for the TX core. A value of 1 enables test mode.

Corresponds to MDIO register bit 3.42.3 as defined in Clause 45. Takes second precedence.
ctl_tx_test_pattern_select I tx_mii_clk Corresponds to MDIO register bit 3.42.1 as defined in Clause 45.
ctl_tx_data_pattern_select I tx_mii_clk Corresponds to MDIO register bit 3.42.0 as defined in Clause 45.
ctl_tx_test_pattern_seed_a[57:0] I tx_mii_clk Corresponds to MDIO registers 3.34 through to 3.37 as defined in Clause 45.
ctl_tx_test_pattern_seed_b[57:0] I tx_mii_clk Corresponds to MDIO registers 3.38 through to 3.41 as defined in Clause 45.
ctl_tx_test_pattern I tx_mii_clk Scrambled idle Test pattern generation enable for the TX core. A value of 1 enables test mode. Corresponds to MDIO register bit 3.42.7 as defined in Clause 45. Takes third precedence.
stat_tx_fifo_error O tx_mii_clk

Transmit clock compensation FIFO error indicator. A value of 1 indicates the clock compensation FIFO under or overflowed.

If this output is sampled as a 1 in any clock cycle, the corresponding port must be reset to resume proper operation.
stat_rx_fifo_error O rx_clk_out

Receive clock compensation FIFO error indicator. A value of 1 indicates the clock compensation FIFO under or overflowed. This condition only occurs if the PPM difference between the recovered clock and the local reference clock is greater than ±200 ppm.

If this output is sampled as a 1 in any clock cycle, the corresponding port must be reset to resume proper operation.
stat_rx_local_fault O rx_clk_out

A value of 1 indicates the receive decoder state machine is in the RX_INIT state.

This output is level sensitive.
stat_rx_hi_ber O rx_clk_out

High Bit Error Rate (BER) indicator. When set to 1, the BER is too high as defined by the 802.3.

Corresponds to MDIO register bit 3.32.1 as defined in Clause 45.

This output is level sensitive.
stat_rx_block_lock O rx_clk_out

Block lock status for each PCS lane. A value of 1 indicates the corresponding lane has achieved a block lock as defined in Clause 49.

Corresponds to MDIO register bit 3.50.7:0 and 3.51.11:0 as defined in Clause 45.

This output is level sensitive.
stat_rx_error O rx_clk_out

Test pattern mismatch increment. A non-zero value in any cycle indicates how many mismatches occurred for the test pattern in the RX core.

This output is only active when ctl_rx_test_pattern is set to a 1.

This output can be used to generate MDIO register 3.43.15:0 as defined in Clause 45.

This output is pulsed for one clock cycle.
stat_rx_valid_ctrl_code O rx_clk_out Indicates that a PCS block with a valid control code was received.
stat_rx_error_valid O rx_clk_out Increment valid indicator. If this signal is a 1 in any clock cycle, the value of stat_rx_error_valid[0:0] is valid.
stat_rx_bad_code O rx_clk_out

Increment for 64B/66B code violations. This signal indicates the number of 64b/66b words received with an invalid block or if a wrong 64b/66b block sequence was detected.

This output can be used to generate MDIO register 3.33:7:0 as defined in Clause 45.
stat_rx_bad_code_valid O rx_clk_out Increment valid indicator. If this signal is a 1 in any clock cycle, the value of stat_rx_bad_code[0:0] is valid.
stat_rx_framing_err O rx_clk_out Increment value for number of bad sync header bits detected. The value of this bus is only valid in the same cycle that the corresponding stat_rx_framing_err_valid is a 1.
stat_rx_framing_err_valid O rx_clk_out Increment valid indicator. If this signal is a 1 in any clock cycle, the value of stat_rx_framing_err[0:0] is valid.