RS-FEC Functional Description - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID
PG210
Release Date
2024-06-07
Version
4.1 English

The RS-FEC feature of the 10G/25G Subsystem provides error correction capability according to IEEE 802.3 Clause 108 or Schedule 3 of the 25G Ethernet Consortium.

The feature requires the insertion of PCS alignment markers as defined in IEEE 802.3 Table 82-2. Inputs are provided for the alignment markers and also for the value of words between alignment markers.

It is possible to bypass the RS-FEC function by means of the enable signals. This will bypass the RS-FEC function and connect the PCS directly to the transceiver, with the benefit of reduced latency. Refer to 25G IEEE 802.3by Reed-Solomon Forward Error Correction LogiCORE IP Product Guide (PG217) (registration required) for the latest latency performance data in the various bypass modes, defined as follows:

FEC Bypass Correction
The decoder performs error detection without correction, (see IEEE Std 802.3by section 108.5.3.2. The latency is reduced in this mode (see 25G IEEE 802.3by Reed-Solomon Forward Error Correction LogiCORE IP Product Guide (PG217) (registration required) for latency figures).
FEC Bypass Indication
In this mode there is correction of the data but no error indication. An additional signal, rx_hi_ser, is generated in this mode to reduce the likelihood that errors in a packet are not detected. The RS decoder counts the number of symbol errors detected in consecutive non-overlapping blocks of 8192 codewords (see IEEE Std 802.3by section 108.5.3.2). The latency is reduced in this mode.
Decoder Bypass
The RS decoder can be bypassed by setting the IEEE Error indication Low when the correction bypass and indication bypass are High.