Miscellaneous Status/Control Ports - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

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4.1 English

The following table shows the miscellaneous status/control ports.

Table 1. Miscellaneous Status/Control Ports
Name I/O Clock Domain Description
dclk I Refer to Clocking. Dynamic Reconfiguration Port (DRP) clock input. The required frequency is set by providing the value in the GT DRP Clock field in the AMD Vivado™ IDE GT Selection and Configuration tab. This must be a free running input clock.