Ingress - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

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Figure 1. Ingress

The ingress logic does not parse the ingress packets to search for 1588 (PTP) frames. Instead, it takes a timestamp for every received frame and outputs this value to the user logic. The feature is always enabled, but the timestamp output can be ignored if you do not require this function.

Timestamps are filtered after the PCS decoder to retain only those timestamps corresponding to an Start of Packet (SoP). These 80-bit timestamps are output on the system side. The timestamp is valid during the SoP cycle.

The accuracy of the 1588 timestamping of Ethernet frames is dependent on several factors, some of which are outside of the scope of this IP core:

timestamp error = (10/25G IP Core 1588 timestamp error) + (external timestamp sampling error) + (error due to system clock jitter, transceiver uncertainty, other factors)

10/25G IP Core 1588 timestamp error:

  • Ordinary Clock mode: +/- 1 ns (due to granularity of ToD format)
  • Transparent Clock mode: +/- 1 SerDes clock bit time

Factors that influence timestamp accuracy:

  • This IP core requires the user to sample the system timer input and to retime it to the specified clock domain (TX SerDes or RX SerDes). A simple sampling circuit will introduce a +/- 1 SerDes clock error. Greater accuracy can be achieved if the customer implements a custom synchronization design.
  • No compensation for external delays (e.g., transceivers) is done inside the IP core. These delays can be determined and added as an offset.
  • For IP cores with RSFEC, the timing plane is assumed to be outside the RSFEC, and so any variation due to transcoding and checksum insertion on TX is removed by the inverse function on RX. Refer to 802.3-2018 Clause 90.7.
  • For MAC+PCS IP cores with RSFEC, the core compensates for the effects of rate adaptation due to AM insertion.
  • 64b IP cores compensate for half block starts (64B/66B blocks with S4).