25G Supported Features - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID
Release Date
4.1 English
  • Complete Ethernet MAC and PCS functions
  • Designed to Schedule 3 of the 25G Consortium
  • Statistics and diagnostics
  • 66-bit serializer/deserializer (SerDes) interface using the AMD GTY transceiver operating with Asynchronous Gearbox enabled
  • Pause Processing including IEEE std. 802.3 Annex 31D (Priority based Flow Control)
  • Low latency
  • Custom preamble and adjustable Inter Frame Gap
  • Configurable for operation at 10.3125 Gbps (Clause 49)
  • Optional Clause 73 Auto-negotiation
  • Optional Clause 72.6.10 Link Training
  • Optional Clause 74 FEC – shortened cyclic code (2112, 2080)
  • Forward Error Correction (RS-FEC) sublayer (Soft RS-FEC TX, Hard RS-FEC RX option to reduce logic utilization by leveraging the embedded 100G RS-FEC function that exists within the CMAC block in UltraScale+ devices).
  • Optional Clause 108 RS FEC (25 Gbps operation only)
  • PCS only version with 25GMII Interface
  • 64-bit AXI4-Stream Interface
  • Optional AXI4-Lite control and status interface
  • Supports 802.1CM (802.3br/802.1bu) preemption feature for MAC+PCS/PMA 64-bit Base-R