| Signal | Direction | Clock Domain | Description |
|---|---|---|---|
| ts_clk | I | N/A | Free running clock which clocks system timer’s counters |
| ts_rst | I | ts_clk | System timer reset active-High |
| tod_intr | O | ts_clk | Interrupt asserted on 1-PPS event |
| Signal | Direction | Clock Domain | Description |
|---|---|---|---|
| ts_clk | I | N/A | Free running clock which clocks system timer’s counters |
| ts_rst | I | ts_clk | System timer reset active-High |
| tod_intr | O | ts_clk | Interrupt asserted on 1-PPS event |