Simulation Speed Up - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

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4.1 English

The example design contains wait timers. A `define SIM_SPEED_UP is available to improve simulation time by speeding up these wait times.SIM_SPEED_UP is only available when running RTL simulation. It is not available when running simulation with post synthesis or post implementation netlist.


Use the vlogan option: +define+SIM_SPEED_UP.


Use the vlog option: +define+SIM_SPEED_UP.

Vivado Simulator

Use the xvlog option: -d SIM_SPEED_UP.

Questa Advanced Simulator

Use the vlog option: +define+SIM_SPEED_UP.

Riviera- Pro Simulator

Use the vlog option: +define+SIM_SPEED_UP.

Xcelium Parallel Simulator

Use the xmvlog option: +define+SIM_SPEED_UP .

Note: The core must be simulated with fs resolution.

RS-FEC Enabled Configuration Simulation

For faster simulation, apply SIM_SPEED_UP and deselect the Use Precompiled IP simulation libraries check box in the Settings window, as shown in the following figures. If this is not done, the simulation can run for a long time, timing out with an error.

Figure 1. Use Precompiled IP Simulation Libraries Disabled
Figure 2. SIM_SPEED_UP Enabled