IEEE Clause 108 (RS-FEC) Integration - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID
Release Date
4.1 English

If you want to include IEEE clause 108 RS-FEC soft IP (for error correction) in between 25G Ethernet IP and the GT, you must select the Include Clause 108 (RS-FEC) check box in the Configuration tab. This option is available for 25G line rate only.

Figure 1. RS-FEC Integration in between 25G and GT

This feature enables the IEEE Clause108 RS-FEC soft IP component instantiated between the 25G core and the GT. The TX SerDes lines from the 25G core will be input to the RS-FEC soft IP for forward error correction encoding. The output from the RS-FEC module is then fed to GT. Similarly, the RX SerDes lines from the GT will be fed to the RS-FEC module for error correction decoding and then to the 25G core.

Refer to the 25G IEEE 802.3by Reed-Solomon Forward Error Correction LogiCORE IP Product Guide (PG217) (registration required) for IEEE clause 108 Reed-Solomon Forward Error Correction for the LogiCORE™ IP core and its functionality.