Ports Added
-
stat_rx_status -
axi_ctl_core_mode_switch_* -
rx_mii_clk -
tx_mii_clk -
clk
Ports Deleted
tx_ptp_pcslane_out
Port Changes
- Added 32-bits to
tx_axis_tdata_*andrx_axis_tdata_* - Updated bus sizes for many signals
- Updated bus sizes of
tx_axis_tdata_*andrx_axis_tdata_*. - Added 32/64-bit to
tx_clk_out_*andtx_mii_out_*. - Added 32 bits to
rx_serdes_data_out_*andtx_serdes_data_in_*. - Replaced "Ethernet MAC+PCS/PMA" with “Ethernet MAC+PCS/PMA-32/64-bit” in most of the signals in Core xci Top Level Port List.
- Inserted "or Ethernet MAC" in most of the signals in Core xci Top Level Port List.
- Updated descriptions of the following:
-
rx_axis_tdata[63 or 31:0] -
rx_axis_tkeep[7 or 3:0] -
ctl_rx_ignore_fcs -
ctl_rx_max_packet_len[14:0] -
ctl_rx_min_packet_len[7:0] -
stat_rx_undersize -
stat_rx_fragment -
stat_tx_total_bytes[3:0] -
stat_tx_frame_error -
ctl_tx_pause_quanta[8:0][15:0] -
ctl_tx_pause_refresh_timer[8:0][15:0] -
ctl_an_nonce_seed[7:0] -
rx_mii_clk -
tx_mii_d_* -
tx_mii_c_* -
rx_mii_d_* -
rx_mii_c_*
-
Registers Added
- USER_REG_1: 0188
- CORE_SPEED_REG:018C
Register Changes
- Added Bit 1 to CORE_SPEED_REG: 0180.
- Added note for Bits 1 and 2 to STAT_TX_STATUS_REG1: 0400.
- Modified notes for most of the registers in Configuration Register Map 10G/25G Ethernet Subsystem, Status Register Map for 10G/25G Ethernet Subsystem, and Statistics Counters.