Ethernet Specific Checks - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID
Release Date
4.1 English

A number of issues can commonly occur during the first hardware test of an 10G/25G High Speed Ethernet Subsystem. These should be checked as indicated below.

It is assumed that the 10G/25G Ethernet Subsystem has already passed all simulation testing that is being implemented in hardware. This is a prerequisite for any kind of hardware debug.

The usual sequence of debugging is to proceed in the following sequence:

  1. Clean up signal integrity.
  2. Ensure that the SerDes achieves clock data recovery (CDR) lock.
  3. Check that the 10G/25G Ethernet Subsystem IP has achieved word sync.
  4. Proceed to Interface and Protocol debug.