GT_WIZ_CONTROL_REG: 0154 - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

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4.1 English
Note: Applies to Versal devices only.
Table 1. GT_WIZ_CONTROL_REG: 0154
Bits Default Type Signal
2:0 3'b000 RW gtwiz_loopback
7:3 5'b00000 RW gtwiz_txprecursor
12:8 5'b00000 RW gtwiz_txpostprecursor
19:13 7'b0000000 RW gtwiz_txmainprecursor
20 1'b0 RW gtwiz_rxcdrhold
  1. Bit description mentioned (for gtwiz_txprecursor, gtwiz_txpostcursor, gtwiz_txmaincursor, gtwiz_rxcdrhold) is valid for non-GTM Versal devices only.
  2. For Versal GTM devices, valid bit description is:bits [8:3] for gtwiz_txprecursor, [14:9] for gtwiz_txpostcursor, [21:15] for gtwiz_txmaincursor, and bit [22] of register is for gtwiz_rxcdrhold.
  3. For more details, refer to Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002).