10G/25G MAC with PCS/PMA Clocking - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID
PG210
Release Date
2023-11-10
Version
4.1 English

The clocking architecture for the 10/25G MAC with PCS/PMA clocking is illustrated below. This version of the subsystem includes FIFOs in the RX. There are three clock domains in the datapath, as illustrated by the dashed lines in the following figure.

Figure 1. 10G/25G MAC with PCS/PMA Clocking
refclk_p0, refclk_n0, tx_serdes_refclk
The refclk differential pair is required to be an input to the FPGA. The example design includes a buffer to convert this clock to a single-ended signal refclk, which is used as the reference clock for the GT block. The tx_serdes_refclk is directly derived from refclk. refclk must be chosen so that the tx_serdes_refclk meets the requirements of 802.3, which is within 100 ppm of 390.625 MHz for 25G, 156.25 MHz for 64-bit 10G, and 312.5 MHz for 32-bit 10G.
tx_clk_out
This clock is used for clocking data into the TX AXI4-Stream Interface and it is also the reference clock for the TX control and status signals. It is the same frequency as tx_serdes_refclk.
rx_clk_out
The rx_clk_out output signal is presented as a reference for the RX control and status signals processed by the RX core. It is the same frequency as the rx_serdes_clk.
rx_clk
The rx_clk is available as rx_core_clk is the input clk for RX core. This to you, which you must drive from the example design. You should drive the rx_core_clk with frequency that is equal to the tx_clk. When FIFO is enabled, the most preferred mode of operation for system side datapath is to connect the tx_clk_out to rx_core_clk. When connected in this manner, the RX AXI4-Stream Interface and the TX AXI4-Stream Interface are on the same clock domain. When FIFO is disabled, rx_core_clk must be driven by rx_clk_out/rx_serdes_clk.
dclk
The dclk signal must be a convenient stable clock. It is used as a reference frequency for the GT helper blocks which initiate the GT itself. In the example design, a typical value is 75 MHz, which is readily derived from the 300 MHz clock available on the VCU107 evaluation board.
Note: The actual frequency must be known to the GT helper blocks for proper operation.