AXI4-Lite Interface - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)
Document ID
PG210
Release Date
2024-06-07
Version
4.1 English
Table 1. AXI4-Lite Interface
Signal Direction Clock Domain Description
s_axi_aclk I N/A AXI4-Lite interface clock
s_axi_aresetn I s_axi_aclk AXI4-Lite interface reset
s_axi_awaddr[31:0] I s_axi_aclk Write address
s_axi_awvalid I s_axi_aclk Write address Valid
s_axi_awready O s_axi_aclk Write address Ready
s_axi_wdata[31:0] I s_axi_aclk Write data
s_axi_wstrb[3:0] I s_axi_aclk Write data byte valid. Tie to 4’hF
s_axi_wvalid I s_axi_aclk Write valid
s_axi_wready O s_axi_aclk Write ready
s_axi_bresp O s_axi_aclk Write response
s_axi_bvalid O s_axi_aclk Write response valid
s_axi_bready I s_axi_aclk Write response ready
s_axi_araddr[31:0] I s_axi_aclk Read address
s_axi_arvalid I s_axi_aclk Read address valid
s_axi_arready O s_axi_aclk Read address ready
s_axi_rdata[31:0] O s_axi_aclk Read data
s_axi_rresp O s_axi_aclk Read response
s_axi_rvalid O s_axi_aclk Read data valid
s_axi_rready I s_axi_aclk Read ready