Data Lane Mapping - RX - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID
PG210
Release Date
2023-11-10
Version
4.1 English

For receive data, rx_axis_tdata[63:0], the port is logically divided into lane 0 to lane 7. See the following table.

Table 1. rx_axis_tdata Lanes
Lane/rx_axis_tkeep rx_axis_tdata[63:0] bits
0 7:0
1 15:8
2 23:16
3 31:24
4 39:32
5 47:40
6 55:48
7 63:56