AXI4-Stream Interface - TX - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)
Document ID
PG210
Release Date
2024-06-07
Version
4.1 English

The following table shows the AXI4-Stream transmit interface signals.

Table 1. AXI4-Stream Transmit Interface Signal
Name I/O Clock Domain Description
tx_axis_tdata[63:0] I clk AXI4-Stream Data
tx_axis_tkeep[7:0] I clk AXI4-Stream Data Control.
tx_axis_tlast I clk AXI4-Stream signal indicating End of Packet.
tx_axis_tvalid I clk AXI4-Stream Data Valid.
tx_axis_tuser I clk AXI4-Stream User Sideband interface signal.

1 indicates a bad packet

0 indicates a good packet
tx_axis_tready O clk AXI4-Stream acknowledge signal to indicate to start the Data transfer
tx_parityin[7:0] I clk AXI4-Stream user-generated parity. Follows the same data lane mapping as tx_axis_tkeep.