This interface is used to connect to the physical layer, where this is a separate device or implemented in the FPGA beside the Ethernet MAC core. The following table shows the port associated with this interface.
| Name | I/O | Clock Domain | Description |
|---|---|---|---|
| rx_mac_mii_d[63:0]/rx_mii_d | I | rx_mii_clk | Receive Data from PHY |
| rx_mac_mii_c[7:0]/rx_mii_c | I | rx_mii_clk | Receive Control from PHY |
| rx_mac_mii_clk/rx_mii_clk | I | Received clock connected from PHY | |
| rx_mac_mii_reset/rx_mii_reset | I | rx_mii_clk | Reset signal received from PHY |
| tx_mac_mii_d[63:0]/tx_mii_d | O | tx_mii_clk | Transmit Data to PHY |
| tx_mac_mii_c[7:0]/tx_mii_c | O | tx_mii_clk | Transmit Control to PHY |
| tx_mac_mii_clk/tx_mii_clk | O | XGMII output clock sent to external PHY | |
| tx_mac_mii_reset/tx_mii_reset | O | tx_mii_clk | Reset signal sent to external PHY |