PCS/PMA 32-bit Clocking - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

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4.1 English
refclk_p0, refclk_n0, rx_serdes_refclk
The refclk differential pair is required to be an input to the FPGA. The example design includes a buffer to convert this clock to a single-ended signal refclk, which is used as the reference clock for the GT block. Note that refclk must be chosen so that the tx_clk_out meets the requirements of IEEE 802.3, which is within 100 ppm of 312.5 MHz for 10G.
The tx_clk_out is an output You must synchronize the TX path mii bus to this clock output. All TX control and status signals are referenced to this clock.
The rx_serdes_clk is derived from the incoming data stream within the GT block. The incoming data stream is processed by the RX core in this clock domain.
The rx_clk_out output signal is presented as a reference for the RX control and status signals processed by the RX core. It is the same frequency as the rx_serdes_clk.
The dclk signal must be a convenient, stable clock. It is used as a reference frequency for the GT helper blocks which initiate the GT itself. In the example design, a typical value is 100 MHz, which is readily derived from the 300 MHz clock available on the VCU107 evaluation board. The actual frequency must be known to the GT helper blocks for proper operation.