| Name | Size | I/O | Description |
|---|---|---|---|
| ctl_tx_enable_* | 1 | I |
TX Enable. This signal is used to enable the transmission of data when it is sampled as a 1. When sampled as a 0, only idles are transmitted by the core. This input should not be set to 1 until the receiver it is sending data to (that is, the receiver in the other device) is fully aligned and ready to receive data (that is, the other device is not sending a remote fault condition). Otherwise, loss of data can occur. If this signal is set to 0 while a packet is being transmitted, the current packet transmission is completed and then the core stops transmitting any more packets. Note: This port is available when
Include AXI4-Lite is
not selected and Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| ctl_tx_send_rfi_* | 1 | I |
Transmit Remote Fault Indication (RFI) code word. If this input is sampled as a 1, the TX path only transmits Remote Fault code words. This input should be set to 1 until the RX path is fully aligned and is ready to accept data from the link partner. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| ctl_tx_send_lfi_* | 1 | I |
Transmit Local Fault Indication (LFI) code word. Takes precedence over RFI. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| ctl_tx_send_idle_* | 1 | I |
Transmit Idle code words. If this input is sampled as a 1, the TX path only transmits Idle code words. This input should be set to 1 when the partner device is sending Remote Fault Indication (RFI) code words. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| ctl_tx_fcs_ins_enable_* | 1 | I |
Enable FCS insertion by the TX core. If this bit is set to 0, the core does not add FCS to the packet. If this bit is set to 1, the HSEC core calculates and adds the FCS to the packet. This input cannot be changed dynamically between packets. Note: This port is available when
Include AXI4-Lite is
not selected and Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| ctl_tx_ignore_fcs_* | 1 | I | Enable FCS error checking at the interface by the TX core. This
input only has effect when ctl_tx_fcs_ins_enable is Low. If this
input is Low and a packet with bad FCS is being transmitted, it is
not binned as good. If this input is High, a packet with bad FCS is
binned as good. The error is flagged on the signals stat_tx_bad_fcs and stomped_fcs, and the packet is transmitted as it was received. Statistics are reported as if there was no FCS error. Note: This port is available when
Include AXI4-Lite
is not selected and Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| ctl_tx_test_pattern_* | 1 | I | Scrambled idle test-pattern generation enable for the TX core. A
value of 1 enables test mode as defined in Clause 49. Corresponds to
MDIO register bit 3.42.7 as defined in Clause 45. Note: This port is available when
Include AXI4-Lite
is not selected in the Configuration tab.
|
| ctl_tx_test_pattern_enable_* | 1 | I | Test pattern enable for the TX core. A value of 1 enables test mode.
Corresponds to MDIO register bit 3.42.2 as defined in Clause 45.
Takes second precedence. Note: This port is available when
Include AXI4-Lite
is not selected in the Configuration tab.
|
| ctl_tx_test_pattern_select_* | 1 | I | Corresponds to MDIO register bit 3.42.1 as
defined in Clause 45. Note: This port
is available when Include
AXI4-Lite is not selected in the Configuration
tab.
|
| ctl_tx_data_pattern_select_* | 1 | I | Corresponds to MDIO register bit 3.42.0 as
defined in Clause 45. Note: This port
is available when Include
AXI4-Lite is not selected in the Configuration
tab.
|
| ctl_tx_test_pattern_seed_a_* | 58 | I | Corresponds to MDIO registers 3.34 through to
3.37 as defined in Clause 45. Note: This port is available when Include
AXI4-Lite is not selected in the Configuration
tab.
|
| ctl_tx_test_pattern_seed_b_* | 58 | I | Corresponds to MDIO registers 3.38 through to
3.41 as defined in Clause 45. Note: This port is available when Include
AXI4-Lite is not selected in the Configuration
tab.
|
| ctl_tx_prbs31_test_pattern_enable_* | 1 | I | Corresponds to MDIO register bit 3.42.4 as defined in Clause 45.
Takes first precedence. Note: This port is available when
Include AXI4-Lite
is not selected in the GT Selection and Configuration tab and
Select Core is
PCS/PMA 64-bit in
the Configuration tab.
|
| ctl_tx_ipg_value_* | 4 | I | This signal can be optionally present. The
ctl_tx_ipg_value defines the target average minimum Inter Packet Gap
(IPG, in bytes) inserted between rx_serdes_clk packets. Typical
value is 12. The ctl_tx_ipg_value can also be programmed to a value
in the 0 to 7 range, but in that case, it is interpreted as meaning
"minimal IPG", so only Terminate code word IPG is inserted; no Idles
are ever added in that case and that produces an average IPG of
around 4 bytes when random-size packets are transmitted. Note: This port is available when
Include AXI4-Lite
is not selected in the Configuration tab and Select Core is
Ethernet
MAC+PCS/PMA-32/64-bit and Include FIFO Logic is enabled
in the MAC Options tab.
|
| ctl_tx_custom_preamble_enable_* | 1 | I | When asserted, this signal enables the use of
tx_preamblein as a custom preamble instead of inserting a standard
preamble. Note: This port is
available when Include
AXI4-Lite is not selected in the Configuration
tab and Select Core is
Ethernet
MAC+PCS/PMA-32/64-bit and the Include FIFO Logic is disabled
in the MAC Options tab or Select Core is Ethernet MAC.
|
| ctl_tx_parity_err_response_* | 1 | I | Parity error response by the TX Core. If this bit is set to 0, the core does not take any action if any parity errors are detected. If this bit is set to 1, the core stomps the outgoing FCS (i.e., bit-wise inverse) and asserts stat_tx_bad_fcs. |
| stat_tx_bad_parity_* | 1 | O | Increment on any clock cycle where the user-generated parity is calculated as incorrect by the TX parity checking logic. |
| stat_tx_local_fault_* | 1 | O | A value of 1 indicates the transmit encoder state machine is in the TX_INIT state. This output is level sensitive. |
| stat_tx_fifo_error_* | 1 | O | Indicates when TX FIFO goes into an underflow
or overflow condition. Note: This port
is available when Select
Core is Ethernet
PCS/PMA in the Configuration tab.
|
| stat_tx_total_bytes_* | 5 | O | Increment for the total number of bytes transmitted. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_tx_total_packets_* | 1 | O | Increment for the total number of packets transmitted. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_tx_total_good_bytes_* | 14 | O | Increment for the total number of good bytes transmitted. This value
is only non-zero when a packet is transmitted completely and
contains no errors. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_tx_total_good_packets_* | 1 | O | Increment for the total number of good packets transmitted. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_tx_bad_fcs_* | 1 | O | Increment for packets greater than 64 bytes that have FCS
errors. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_tx_packet_64_bytes_* | 1 | O | Increment for good and bad packets transmitted that contain 64
bytes. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_tx_packet_65_127_bytes_* | 1 | O | Increment for good and bad packets transmitted that contain 65 to
127 bytes. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_tx_packet_128_255_bytes_* | 1 | O | Increment for good and bad packets transmitted that contain 128 to
255 bytes. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_tx_packet_256_511_bytes_* | 1 | O | Increment for good and bad packets transmitted that contain 256 to
511 bytes. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_tx_packet_512_1023_bytes_* | 1 | O | Increment for good and bad packets transmitted that contain 512 to
1,023 bytes. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_tx_packet_1024_1518_bytes_* | 1 | O | Increment for good and bad packets transmitted that contain 1,024 to
1,518 bytes. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_tx_packet_1519_1522_bytes_* | 1 | O | Increment for good and bad packets transmitted that contain 1,519 to
1,522 bytes. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_tx_packet_1523_1548_bytes_* | 1 | O | Increment for good and bad packets transmitted that contain 1,523 to
1,548 bytes. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_tx_packet_1549_2047_bytes_* | 1 | O | Increment for good and bad packets transmitted that contain 1,549 to
2,047 bytes. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_tx_packet_2048_4095_bytes_* | 1 | O | Increment for good and bad packets transmitted that contain 2,048 to
4,095 bytes. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_tx_packet_4096_8191_bytes_* | 1 | O | Increment for good and bad packets transmitted that contain 4,096 to
8,191 bytes. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_tx_packet_8192_9215_bytes_* | 1 | O | Increment for good and bad packets transmitted that contain 8,192 to
9,215 bytes. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_tx_packet_small_* | 1 | O | Increment for all packets that are less than 64 bytes long. Packets
that are less than 64 bytes are not transmitted. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_tx_packet_large_* | 1 | O | Increment for all packets that are more than 9,215 bytes long. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|
| stat_tx_frame_error_* | 1 | O | Increment for packets with tx_axis_tuser set to indicate an End of
Packet (EOP) abort or frames aborted by de-asserting tvalid without
tlast. Note: This
port is available when Select
Core is Ethernet
MAC+PCS/PMA-32/64-bit or Ethernet MAC in the
Configuration tab.
|