IEEE 802.3 Clause 108 RS-FEC Interface - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)
Document ID
PG210
Release Date
2024-06-07
Version
4.1 English

The following table shows the IEEE 802.3 Clause 108 RS-FEC Control/Status and Statistics signals.

Table 1. IEEE 802.3 Clause 108 (RS-FEC) Control/Status/Statistics Signals
Signal I/O Clock Description
ctl_rx_rsfec_enable_correction I rx_serdes_clk

Equivalent to MDIO register 1.200.0

  • 0: Decoder performs error detection without error correction (see IEEE 802.3by Clause 91.5.3.3).
  • 1: the decoder also performs error correction.
ctl_rx_rsfec_enable_indication I rx_serdes_clk

Equivalent to MDIO register 1.200.1

  • 0: Bypass the error indication function(see IEEE Std 802.3by Clause 91.5.3.3).
  • 1: Decoder indicates errors to the PCS sublayer
ctl_rsfec_enable I rx_serdes_clk

Enable RS-FEC function.

Note: Some variants of the 10G/25G Ethernet IP Subsystem can have separate TX and RX enable signals.
ctl_rsfec_ieee_error_indication_mode I rx_serdes_clk

This signal indicates that the core conforms to the IEEE RS-FEC specification.

  • 1: Core conforms to the IEEE RS-FEC specification.
  • 0: If ctl_rx_rsfec_enable_correction and ctl_rx_rsfec_enable_indication are set to zero, the RS decoder is bypassed.
ctl_rsfec_consortium_25g I rx_serdes_clk

This signal switches between IEEE Clause 108 and 25G Ethernet Consortium modes

  • 1 = 25G Consortium specification mode;
  • 0 = IEEE 802.3 by mode
Note: Some variants of the 10G/25G Subsystem can have individual RX and TX consortium signals.
stat_rx_rsfec_hi_ser O rx_serdes_clk

Indicates high symbol error.

Set to 1 if the number of RS-FEC symbol errors in a window of 8192 codewords exceeds the threshold of 417.

Set to 0 otherwise
stat_rx_rsfec_lane_alignment_status O rx_serdes_clk A value of 1 indicates that the RX RS-FEC block has achieved alignment on the data from the transceiver.
stat_rx_rsfec_corrected_cw_inc O rx_serdes_clk Increment for corrected errors
stat_rx_rsfec_uncorrected_cw_inc O rx_serdes_clk Increment for uncorrected errors
stat_rx_rsfec_err_count0_inc[2:0] O rx_serdes_clk Increment for detected errors
stat_tx_rsfec_lane_alignment_status O tx_serdes_clk A value of 1 indicates that the TX RS-FEC block has achieved alignment on the incoming PCS data.