The following table shows the miscellaneous status and control signals.
| Name | I/O | Clock Domain | Description |
|---|---|---|---|
| ctl_rx_process_lfi | I | clk |
When this input is set to 1, the RX core expects and processes LF control codes coming in from the transceiver. When set to 0, the RX core ignores LF control codes coming in from the transceiver. |
| stat_tx_gmii_fifo_unf 1 | O | clk | TX FIFO underflow |
| stat_tx_gmii_fifo_ovf 1 | O | clk | TX FIFO overflow |
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