Software Driver Initialization - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID
PG210
Release Date
2023-11-10
Version
4.1 English
It is recommended that the software drivers follow these steps sequentially to properly initialize the core.
  1. Initialize other elements of the design such that the clocks including ts_clk and tx/rx_phy_clk* are present and stable. Release resets for these clock domains such as ts_rst, tx/rx_phy_rst*.
  2. Configure the TOD_CONFIG register:
    1. In Timer or Timer Syncer mode set bit [0] to enable the system timer.
    2. If an external ToD bus (1PPS synchronization and optionally serial seconds input) is to be used, then set bit [1] to 1.
    3. Set the mode bit field [3:2] to the setting matching the intended synchronization method used in your system. For example, if your system uses an external device connected to the External ToD bus (1PPS input and second’s value serial input). The mode field should be set to 0x1.
    4. Finally, enable (set to 1) the appropriate bits of the Port Timer enable bitfield [19:4] to enable the port TX and RX timers.
  3. If the system timer’s initial value is to be set by the software via register programming, an alternative to the external ToD bus interface, then write the appropriate initial values to the software loading registers such as TOD_SW_SEC_0/1 and TOD_SW_NS, TOD_SW_CTIME_0/1. Also, configure any static offset to be loaded by writing the TOD_SEC_SYS_OFFSET_0/1 and TOD_NS_SYS_OFFSET_0 registers.
  4. If the software registers are updated in Step 2, then a write of 1 to the appropriate bits of TOD_SW_LOAD[1:0] triggers the system timer to load software values.
  5. Program the port TX/RX Timer. This includes the period values and any required static offset to the appropriate values by writing to the Port timer’s registers: TX<M>_PERIOD_0/1, RX<M>_PERIOD_0/1, and TX<M>/RX<M>_SYS_OFFSET.
  6. Configure the Timer syncer IP by passing the GUI parameter Core_CONFIGURATION as '1' and pass the resync clock frequency in PS to RESYNC_CLK_PERIOD to generate the required Timer Syncer IP for Soft XXV_Ethernet IP core.

    Example: For xxv Ethernet soft IP, ptp timer syncer IP is configured as following:

    
    
    set_property -dict [ list \
                         CONFIG.AXI4LITE_FREQ {<=:$C_GT_DRP_CLK:>} \
                         CONFIG.CORE_MODE {Timer_Syncer} \
                         CONFIG.ENABLE_EXT_TOD_BUS {0} \
                         CONFIG.ENABLE_HIGH_ACCURACY_MODE {1} \
                         CONFIG.NUM_PORTS {1} \
                         CONFIG.TIMER_FORMAT {Time_of_Day} \
    		     CONFIG.CORE_CONFIGURATION {1} \
    <: if {$C_LINE_RATE == 10} { :>
           <: if {$C_CORE == "Ethernet MAC+PCS/PMA 32-bit" || $C_CORE == "Ethernet PCS/PMA 32-bit"} { :>
                         CONFIG.RESYNC_CLK_PERIOD {3200} \
              <: } else { :>
                         CONFIG.RESYNC_CLK_PERIOD {6400} \
           <: } :>
        <: } else { :>
                         CONFIG.RESYNC_CLK_PERIOD {2560} \
    <: } :>
                         CONFIG.TS_CLK_PERIOD {<=: format "%.3f" [expr $C_SYS_CLK_NS *1] :>} \
                       ] $ptp_1588_timer_syncer_0

Continue step 4 for all Ports (M) present in the design.