| Name | Size | I/O | Description |
|---|---|---|---|
| gt_loopback_in_* | 3 | I | GT loopback input signal. Refer to the GT user guide. Note: This port is available when the
Include GT subcore in
core option is selected in the GT
Selection and Configuration tab.
|
| gt_loopback_out_* | 1 | O | GT loopback output signal from AXI4-Stream register map. Refer to the GT user guide. Note: This port is available when
Include
AXI4-Lite is selected from the
Configuration tab and the Include GT subcore in example design
option is selected in the GT Selection and Configuration
tab.
|
| gt_txp_out | 1 | O | Differential serial GT TX output
Note: For
board-based designs, this port is available when the
Include GT subcore in
core option is selected in the GT
Selection and Configuration tab.
Note: For
part-based designs, this port is available when the
Include GT subcore in
core option and Enable GT Interface for Board Based
Design option are selected in the GT
Selection and Configuration tab.
|
| gt_txn_out | 1 | O | Differential serial GT TX output.
Note: For
board-based designs, this port is available when the
Include GT subcore in
core option is selected in the GT
Selection and Configuration tab.
Note: For
part-based design, this port is available when the
Include GT subcore in
core option and Enable GT Interface for Board Based
Design option is selected in the GT
Selection and Configuration tab.
|
| gt_rxn_in | 1 | I | Differential serial GT RX input.
Note: For
board-based designs, this port is available when the
Include GT subcore in
core option is selected in the GT
Selection and Configuration tab.
Note: For
part-based designs, this port is available when the
Include GT subcore in
core option and Enable GT Interface for Board Based
Design option is selected in the GT
Selection and Configuration tab.
|
| gt_rxp_in | 1 | I | Differential serial GT RX input. Note: For board-based designs, this port
is available when the Include GT subcore in core option is
selected in the GT Selection and Configuration tab.
Note: For
part-based designs, this port is available when the
Include GT subcore in
core option and Enable GT Interface for Board Based
Design option is selected in the GT
Selection and Configuration tab.
|
| gt_rxp_in_0 | 1 | I | Differential serial GT RX input for lane 0. Note: This port is available when the
Include GT subcore in
core option is selected in the GT
Selection and Configuration tab.
|
| gt_rxn_in_0 | 1 | I | Differential serial GT RX input for lane 0. Note: This
port is available when the Include GT
subcore in core option is selected in
the GT Selection and Configuration tab.
|
| gt_rxp_in_1 | 1 | I | Differential serial GT RX input for lane 1. Note: This port is available
when Num of Cores is >1
and the Include GT subcore in
core option is selected in the GT
Selection and Configuration tab.
|
| gt_rxn_in_1 | 1 | I | Differential serial GT RX input for lane 1. Note: This port is available
when Num of Cores is >1
and the Include GT subcore in
core option is selected in the GT
Selection and Configuration tab.
|
| gt_rxp_in_2 | 1 | I | Differential serial GT RX input for lane 2. Note: This port is available when Num of Cores
is >2 and the Include GT subcore in core option is selected
in the GT Selection and Configuration tab.
|
| gt_rxn_in_2 | 1 | I |
Differential serial GT RX input for lane 2. Note: This port is available when
Num of Cores is >2
and the Include GT subcore in
core option is selected in the GT
Selection and Configuration tab.
|
| gt_rxp_in_3 | 1 | I | Differential serial GT RX input for lane 3. Note: This port is available
when Num of Cores is >3
and the Include GT subcore in
core option is selected in the GT
Selection and Configuration tab.
|
| gt_rxn_in_3 | 1 | I | Differential serial GT RX input for lane 3. Note: This port is available
when Num of Cores is >3
and the Include GT subcore in
core option is selected in the GT
Selection and Configuration tab.
|
| gt_txp_out_0 | 1 | O | Differential serial GT TX output for lane 0. Note: This port is available
when the Include GT subcore in
core option is selected in the GT
Selection and Configuration tab.
|
| gt_txn_out_0 | 1 | O | Differential serial GT TX output for lane 0. Note: This port is available
when the Include GT subcore in
core option is selected in the GT
Selection and Configuration tab.
|
| gt_txp_out_1 | 1 | O | Differential serial GT TX output for lane 1. Note: This port is available
when Num of Cores is >1
and the Include GT subcore in
core option is selected in the GT
Selection and Configuration tab.
|
| gt_txn_out_1 | 1 | O | Differential serial GT TX output for lane 1. Note: This port is available
when Num of Cores is >1
and the Include GT subcore in
core option is selected in the GT
Selection and Configuration tab.
|
| gt_txp_out_2 | 1 | O | Differential serial GT TX output for lane 2. Note: This port is available
when Num of Cores is >2
and the Include GT subcore in
core option is selected in the GT
Selectionand Configuration tab.
|
| gt_txn_out_2 | 1 | O | Differential serial GT TX output for lane 2. Note: This port is available
when Num of Cores is >2
and the Include GT subcore in
core option is selected in the GT
Selection and Configuration tab.
|
| gt_txp_out_3 | 1 | O | Differential serial GT TX output for lane 3. Note: This port is available
when Num of Cores is >3
and the Include GT subcore in
core option is selected in the GT
Selection and Configuration tab.
|
| gt_txn_out_3 | 1 | O | Differential serial GT TX output for lane 3. Note: This port is available
when Num of Cores is >3
and the Include GT subcore in
core option is selected in the GT
Selection and Configuration tab.
|
| gtwiz_loopback_* | 3 | O | GT loopback output signal from AXI4-Lite register map. (Versal devices only). See the
appropriate GT user guide. Note: This port is available when the
Include GT subcore in
example design option is selected in
the GT Selection and Configuration tab and the AXI4-Lite interface is selected
from configuration tab.
Note: You must manually connect this
signal in the board design.
|
| gtwiz_tx_rate_* | 8 | O | GT TX line rate select from the AXI4-Lite register map. (Versal devices only). See the
appropriate GT user guide. Note: This port is available when the
Include GT subcore in
example design option is selected in
the GT Selection and Configuration tab and the AXI4-Lite interface is selected
from configuration tab.
|
| gtwiz_rx_rate_* | 8 | O | GT TX line rate select from the AXI4-Lite register map. (Versal devices only). See the appropriate GT user
guide. Note: This port is
available when the Include
GT subcore in example design option is
selected in the GT Selection and Configuration tab and the
AXI4-Lite interface is
selected from Configuration tab.
|
| rxgearboxslip_in_* | 1 | O | Rxgearboxslip signal from core to GT. Note: This port is available when the
Include GT subcore in
example design option is selected in
the GT Selection and Configuration tab and GT type is not
GTM.
|
| temperature | 10 | I | For more information, see
Virtex UltraScale+
FPGAs GTM Transceivers Wizard LogiCORE IP Product Guide (PG315). Note: This port is available when the
Include GT subcore in
core option is selected in the GT
Selection and Configuration tab and GT type is
GTM.
|
| rxdatavalid_out_* | 2 | I |
RX data valid signal from GT to core. Note: This port is available when the
Include GT subcore in
example design option is selected in
the GT Selection and Configuration tab and GT type is not
GTM.
|
| rx_serdes_data_out_* | 32/64/128 | I | RX data signal from GT to core. Note: This port is available when the
Include GT subcore in
example design option is selected in
the GT Selection and Configuration tab and GT type is not
GTM.
The data width is 32/64 bits for 10G configuration and 128 bits for 25G configuration. |
| rxdata_out_* | 256 | I | RX data signal from GT to core. Note: This port is available when the
Include GT subcore in example
design option is selected in the GT
Selection and Configuration tab and GT type is
GTM.
|
| rxheader_out_* | 6 | I | RX header signal from GT to core. Note: This port is available when the
Include GT subcore in
example design option is selected in
the GT Selection and Configuration tab and GT type is not
GTM.
|
| rxheadervalid_out_* | 2 | I | RX header valid signal from GT to core. Note: This port is available when the
Include GT subcore in example
design option is selected in the GT
Selection and Configuration tab and GT type is not
GTM.
|
| tx_serdes_data_in_* | 32/64/128 | O | TX data signal from core to GT. Note: This port is available when the
Include GT subcore in example
design option is selected in the GT
Selection and Configuration tab and GT type is not GTM.
The data width is 32/64 bits for 10G configuration and 128 bits for 25G configuration. |
| txdata_in_* | 256 | O | TX data signal from core to GT. Note: This port is available when the
Include GT subcore in example
design option is selected in the GT
Selection and Configuration tab and GT type is
GTM.
|
| mst_tx_resetdone_* | 1 | I | TX master resetdone signal from GT to Core indicates lane0 status. (Versal devices only). |
| mst_rx_resetdone_* | 1 | I | RX master resetdone signal from GT to Core indicates lane0 status. (Versal devices only). |
| tx_pma_resetdone_* | 1 | I | TX PMA resetdone signal from GT to Core indicates lane0 status. (Versal devices only). |
| rx_pma_resetdone_* | 1 | I | RX PMA resetdone signal from GT to Core indicates lane0 status. (Versal devices only). |
| mst_tx_reset_* | 1 | O | TX master reset output signal from Core to GT of Lane0. (Versal devices only). |
| mst_rx_reset_* | 1 | O | RX master reset output signal from Core to GT of Lane0. (Versal devices only). |
| txuserrdy_out_* | 1 | O | TX user ready output signal from Core (reset Interface IP) to GT of Lane0. (Versal devices only). |
| mst_tx_dp_reset_* | 1 | O | TX reset output signal from GT reset IP to the core (Versal devices only). |
| mst_rx_dp_reset_* | 1 | O | RX reset output signal from GT reset IP to the core (Versal devices only). |
| rxuserrdy_out_* | 1 | O | RX user ready output signal from Core (reset Interface IP) to GT of Lane0. (Versal devices only). |
| tx_resetdone_out_* | 1 | O | TX user ready output signal from Core to example design. (Versal devices only). |
| rx_resetdone_out_* | 1 | O | RX user ready output signal from Core to example design. (Versal devices only). |
| txheader_in_* | 6 | O | TX header signal from core to GT. Note: This port is available when the
Include GT subcore in
example design option is selected in
the GT Selection and Configuration tab.
|