IEEE 802.3 Clause 74 FEC Interface - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)

Document ID: PG210
Release Date: 2024-06-07
Version: 4.1 English

The following table shows the IEEE 802.3 Clause 74 FEC Control/Status and Statistics signals.

Table 1. IEEE 802.3 Clause 74 FEC Interface Control/Status/Statistics Signals
Signal	I/O	Clock	Description
ctl_fec_tx_enable	I	tx_serdes_clk	Asserted to enable the clause 74 FEC encoding on the transmitted data.
ctl_fec_rx_enable	I	rx_serdes_clk	Asserted to enable the clause 74 FEC decoding of the received data.
ctl_fec_enable_error_to_pcs	I	rx_serdes_clk	Clause 74 FEC enable error to PCS.
stat_fec_inc_correct_count[3:0]	O	rx_serdes_clk	This signal will be asserted roughly every 32 words, while the ctl_rx_fec_enable is asserted, if the FEC decoder detected and corrected a bit errors in the corresponding frame.
stat_fec_inc_cant_correct_count[3:0]	O	rx_serdes_clk	This signal will be asserted roughly every 32 words, while the ctl_rx_fec_enable is asserted, if the FEC decoder detected bit.
stat_fec_lock_error[3:0]	O	rx_serdes_clk	This signal is asserted if the FEC decoder has been unable to detect the frame boundary after about 5 ms. It is cleared when the frame boundary is detected.
stat_fec_rx_lock[3:0]	O	rx_serdes_clk	This signal is asserted while the ctl_fec_rx_enable is asserted when the FEC decoder detects the frame boundary.