GT_RESET_REG: 0000 - 4.1 English

10G/25G High Speed Ethernet Subsystem Product Guide (PG210)
Document ID
PG210
Release Date
2024-06-07
Version
4.1 English
Table 1. GT_RESET_REG: 0000
Bits Default Type Signal
0 0 RW

ctl_gt_reset_all

This is a clear on write register.
1 0 RW ctl_gt_rx_reset
2 0 RW ctl_gt_tx_reset