Ports in the following table are available when Include AXI4-Lite is selected on the Configuration tab.
Name | Size | I/O | Description |
---|---|---|---|
s_axi_aclk_* | 1 | I | AXI clock signal |
s_axi_aresetn_* | 1 | I | AXI reset signal |
pm_tick_* | 1 | I | PM tick user input |
s_axi_awaddr_* | 32 | I | AXI write address |
s_axi_awvalid_* | 1 | I | AXI write address valid |
s_axi_awready_* | 1 | O | AXI write address ready |
s_axi_wdata_* | 32 | I | AXI write data |
s_axi_wstrb_* | 4 | I | AXI write strobe. This signal indicates which byte lanes hold valid data. |
s_axi_wvalid_* | 1 | I | AXI write data valid. This signal indicates that valid write data and strobes are available. |
s_axi_wready_* | 1 | O | AXI write data ready |
s_axi_bresp_* | 2 | O |
AXI write response. This signal indicates the status of the write transaction. 'b00 = OKAY ‘b01 = EXOKAY ‘b10 = SLVERR ‘b11 = DECERR |
s_axi_bvalid_* | 1 | O | AXI write response valid. This signal indicates that the channel is signaling a valid write response. |
s_axi_bready_* | 1 | I | AXI write response ready. |
s_axi_araddr_* | 32 | I | AXI read address |
s_axi_arvalid_* | 1 | I | AXI read address valid |
s_axi_arready_* | 1 | O | AXI read address ready |
s_axi_rdata_* | 32 | O | AXI read data issued by slave |
s_axi_rresp_* | 2 | O |
AXI read response. This signal indicates the status of the read transfer. ‘b00 = OKAY ‘b01 = EXOKAY ‘b10 = SLVERR ‘b11 = DECERR |
s_axi_rvalid_* | 1 | O | AXI read data valid |
s_axi_rready_* | 1 | I | AXI read ready. This signal indicates the user/master can accept the read data and response information. |