Using an Evaluation Board to Demonstrate SEM Controller Behavior - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

Document ID
PG187
Release Date
2024-06-05
Version
3.1 English

The SEM IP controller is device dependent. When generating the SEM controller IP, you can choose to target evaluation boards. When the following evaluation boards are targeted, the generated IP and system-level example designs are tailored for out-of-the-box hardware bring-up (the device is chosen by selecting the board):

  • AMD Kintex™ UltraScale™ KCU105 Evaluation Platform
  • AMD Virtex™ UltraScale™ VCU108 Evaluation Platform

You can use these designs to build an understanding of the IP behavior and also demonstrate its characteristics.

For a demonstration of the SEM controller behavior on the AMD Zynq™ AMD UltraScale+™ MPSoC ZCU102 Evaluation Platform, see Integrating LogiCORE SEM IP in Zynq UltraScale+ Devices (XAPP1298) and Integrating LogiCORE SEM IP with AXI in Zynq UltraScale+ Devices (XAPP1303).