By design, certain configuration memory bits can change value during design operation. This is frequently the case where logic slice resources are configured to implement LUTRAM functions such as Distributed RAM or Shift Registers. It also occurs when other resource types with Dynamic Reconfiguration Ports are updated during design operation.
The memory bits associated with these resources must be
masked so that they are excluded from CRC and ECC calculations to prevent false error
detections. AMD FPGA devices implement configuration memory masking to prevent
these false error detections. A global control signal, GLUTMASK_B , selects
if masking is enabled or disabled. The controller always enables configuration memory
masking.
UltraScale devices implement fine grain masking at a resource level. This means individual resources, when configured for dynamic operation, have their configuration memory bits masked. Only the required memory bits are masked, without impacting unrelated memory bits. The masked bits are no longer monitored by the controller.
Configuration memory reads of bits associated with masked resources return constant values (either logic one or logic zero). This prevents false error detections. Configuration memory writes to bits associated with masked resources are discarded. This prevents over-writing the contents of dynamic state elements with stale data. A side effect is that error injections into masked resources do not result in error detections.
In many cases (for example, LUTRAM functions) it is possible for you to design to implement data protection on these bits for purposes of soft error mitigation. Another approach is to modify your design to eliminate the use of features that introduce configuration memory masking. LUTROM functions are not be masked by SEM IP, you have to refer to LUT properties for finding the LUT usage details.