Example UART Logs - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

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3.1 English

The following sections provide example logs that are based on the AMD UltraScale+™ FPGAs. These short examples from the SEM IP UART logs are a sample of the observable activity when the IP is configured in Mitigation and Testing mode with the Error Classification feature disabled, except where noted.