Contents of the Xilinx Design Constraints File - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

Document ID
Release Date
3.1 English

Although the XDC delivered with each generated solution shares the same overall structure and sequence of constraints, the contents might vary based on options set at generation. The sections that follow define the structure and sequence of constraints using an AMD Kintex™ UltraScale™ device implementation as an example.