Implementation - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

Document ID
PG187
Release Date
2024-06-05
Version
3.1 English

The example design is not generated by default. The example design is generated by user request and can be opened in a new instance of AMD Vivado™ . This allows you to view and modify the example of various cores being used without touching their own design. To generate the example design, right-click the XCI file under Design Sources and select Open IP Example Design.