Solution Reliability - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

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3.1 English

The system-level design example is analyzed in the following section to provide an estimate of the FIT of the solution itself, as implemented in the FPGA. This analysis method is also appropriate for generating estimates of other circuits implemented in the FPGA.

In this analysis, all features are considered enabled with all signals brought to I/O pins. Virtual Input Output (VIO) core is specifically excluded from analysis, as it is unlikely a production design includes this interactive debug and experimentation capability. As a result, the estimate represents an upper bound.

To calculate the reliability estimation of a design (including SEM IP), use the pre-design (spreadsheet-based) SEU FIT estimation tool. The maximum estimated FIT rate for the SEM IP solution (with all features enabled including all of the helper blocks) is in the following table.

Table 1. Maximum Estimated FIT Rate
Device FIT
UltraScale Monolithic devices 9
UltraScale KU115 (SSI example) 23
UltraScale+ Monolithic devices 3
UltraScale+ SSI devices 6

The estimations above includes the contribution of the configuration RAM and block RAM used by the SEM controller and its system-level design example.