Error Injection Latency - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)
Document ID
PG187
Release Date
2024-06-05
Version
3.1 English

The following table provides error injection latency for a 1-bit configuration frame upset, assuming no throttling on the Monitor Interface.

Table 1. Error Injection Latency When Using Linear Frame Addressing, No Throttling on Monitor Interface
Device Family Error Injection Latency at ICAP_FMax (µs)
UltraScale KU040 50 1
UltraScale+ VU3P 81 1
UltraScale+ SSI VU9P 164 1
  1. Measured in hardware.

The error injection latency value given in the previous table changes based on the clock frequency and the number of the configuration frame in the device.