SPI Bus Timing Budget Conclusions - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

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3.1 English

When the SPI flash master helper block and external memory system are present, the SPI bus timing budget must be analyzed to ensure a robust implementation. The result of the analysis helps to confirm that the external memory system is functional, and reveals any constraints it might pose on the maximum frequency of the system-level design example input clock.

Using the example data from the AMD Vivado™ Design Suite timing report for a Kintex UltraScale SEM IP implementation, the memory interface is functional. The most stringent requirement on Tclk is that Tclk ? 9.057 ns, as the memory interface only works when the input clock frequency is 110.412 MHz or lower. Other input clock frequency limits, such as the ICAP maximum clock frequency and the system-level example maximum clock frequency, must also be considered.