IP Facts - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

Document ID
Release Date
3.1 English
AMD LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family 1 AMD UltraScale+™ 1 , AMD UltraScale™
Supported User Interfaces RS-232, SPI
Resources See Resource Utilization
Provided with Core
Design Files Encrypted register transfer level (RTL)
Example Design Verilog
Test Bench N/A
Constraints File Xilinx Design Constraints (XDC)
Simulation Model N/A
Supported S/W Driver 2 N/A
Tested Design Flows 2
Design Entry AMD Vivado™ Design Suite
Simulation N/A
Synthesis Vivado Synthesis
Release Notes and Known Issues Master Answer Record: 63609
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Support web page
  1. For a complete list of supported devices, see the AR 63609.
  2. For the supported versions of third-party tools, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973)