Timing Constraints - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

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3.1 English

The first constraint in this group is for the system clock input for the entire design. The period constraint value is based on options set at generation:

create_clock -name clk -period 125.0 [get_ports clk]

This is followed by constraints to ignore the asynchronous output signals of the ICAP ports:

set_false_path -from [get_pins {example_support_wrapper/example_support/example_cfg/cfg_icape3/CLK}] -to [get_pins {example_support_wrapper/example_support/sem_controller/inst/controller/controller_synchro_icap_prerror/sync_a/D}]
set_false_path -from [get_pins {example_support_wrapper/example_support/example_cfg/cfg_icape3/CLK}] -to [get_pins {example_support_wrapper/example_support/sem_controller/inst/controller/controller_synchro_icap_prdone/sync_a/D}]
set_false_path -from [get_pins {example_support_wrapper/example_support/example_cfg/cfg_icape3/CLK}] -to [get_pins {example_support_wrapper/example_support/sem_controller/inst/controller/controller_synchro_icap_avail/sync_a/D}]

The second set of constraints in this group is for the UART helper block, applying input/output timing constraints the interface. The input and output timing constraints are set at a single clock period.

set_input_delay -clock clk -max -125.0 [get_ports uart_rx]
set_input_delay -clock clk -min 250.0 [get_ports uart_rx]
set_output_delay -clock clk -125.0 [get_ports uart_tx] -max
set_output_delay -clock clk 0 [get_ports uart_tx] -min

The third set of constraints in this group is for the SPI flash master helper block, and is only present when error classification is enabled and this helper block is generated. It applies input/output timing constraints to the interface. The input and output timing is of considerable importance, as the actual timing must be used in the analysis of the SPI bus timing budget. However, there is no hard requirement for input and output timing of the implemented FPGA. It varies based on the selected device and speed grade.

As such, the input and output timing constraints are arbitrarily set at two times the period constraint. The additional constraint to use IOB flip-flops yields substantially better input and output timing than the constraint values suggest. It is the actual timing obtained from the timing report that should be used in the analysis of the SPI bus timing budget, not the constraint value.

set_input_delay -clock clk -max -125.0 [get_ports spi_q]
set_input_delay -clock clk -min 250.0 [get_ports spi_q]
set_output_delay -clock clk -125.0 [get_ports spi_c] -max
set_output_delay -clock clk 0 [get_ports spi_c] -min
set_output_delay -clock clk -125.0 [get_ports spi_d] -max
set_output_delay -clock clk 0 [get_ports spi_d] -min
set_output_delay -clock clk -125.0 [get_ports spi_s_n] -max
set_output_delay -clock clk 0 [get_ports spi_s_n] -min
set_property IOB TRUE [get_cells example_support_wrapper/example_support/example_spi/example_spi_byte/spi_c_ofd]
set_property IOB TRUE [get_cells example_support_wrapper/example_support/example_spi/example_spi_byte/spi_d_ofd]
set_property IOB TRUE [get_cells example_support_wrapper/example_support/example_spi/example_spi_byte/spi_q_ifd]
set_property IOB TRUE [get_cells example_support_wrapper/example_support/example_spi/spi_s_ofd]