SPI Bus Receive Waveform and Timing Budget - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)
Document ID
PG187
Release Date
2024-06-05
Version
3.1 English

The SPI flash device exhibits certain output switching characteristics of its output data with respect to its input clock. This analysis is for data capture at the system-level design example, when receiving data from the SPI flash device.

Figure 1. SPI Flash Device Output Data Switching Characteristics

The following parameters, shown in the previous figure, are defined as the output switching behavior of the SPI flash device:

Tclqv
SPI flash maximum output valid with respect to clock
Tclqx
SPI flash minimum output hold with respect to clock

The analysis assumes minimum propagation delays are zero. This analysis also assumes the following skews are negligible:

  • Skew on input clock distribution to FPGA output and input flip-flops.
  • Skew in PCB level translator channel delays. The level translator on clock and datapaths must be matched for this to be true.
  • Duty cycle distortion.

The following parameters are defined as implementation parameters of the SPI flash master helper block and PCB:

  • Tclk = input clock cycle time (icap_clk )
  • Tqfpga = FPGA output delay with respect to icap_clk
  • Tsfpga = FPGA input setup requirement with respect to icap_clk
  • Thfpga = FPGA input hold requirement with respect to icap_clk
  • Tw1 = FPGA to level translator PCB trace delay
  • Tw2 = Level translator to SPI flash PCB trace delay
  • Tw3 = SPI flash to level translator PCB trace delay
  • Tw4 = Level translator to FPGA PCB trace delay
  • Tdly = Level translator channel delay

The timing path is a two cycle path for the SPI flash master helper block, but a single cycle path to the SPI flash device. For the timing analysis, the clock to out of the SPI flash device is modeled as a combinational delay. Both setup and hold requirements at the FPGA must be considered.

The memory system signaling generated by the SPI flash master helper block implementation is shown in the following figures.

Figure 2. Output Data Capture Timing (Hold Analysis)
Figure 3. Output Data Capture Timing (Setup Analysis)

The hold path analysis is a pass/fail test. The hold path analysis must be calculated using minimum delay values, for which the following relationship must be verified:

Thfpga ≤ Tqfpga,min + Tw1 + Tdly + Tw2 + Tclqx + Tw3 + Tdly + Tw4

Substituting zero as a conservative minimum delay for Tw1 , Tw2 , Tw3 , Tw4 , and Tdly yields:

Thfpga ≤ Tqfpga,min + Tclqx

The setup path analysis must be calculated using maximum delay values:

Tclk ≥ 0.5 × (Tqfpga,max + Tw1 + Tdly + Tw2 + Tclqv + Tw3 + Tdly + Tw4 + Tsfpga )

Example: AMD Vivado™ Design Suite, AMD Kintex™ UltraScale™ FPGA

  • Tclqv = 6 ns (from SPI flash data sheet)
  • Tclqx = 1 ns (from SPI flash data sheet)
  • Tdly = 2.8 ns (from level translator data sheet)
  • Tw1 = 1 ns (from board simulation)
  • Tw2 = 1 ns (from board simulation)
  • Tw3 = 1 ns (from board simulation)
  • Tw4 = 1 ns (from board simulation)

The FPGA timing parameters must be obtained from the timing report from the implementation of the system-level design example in the FPGA targeted for use in the application. To generate the necessary report, use report_timing_summary to generate a report using the min_max option.

The examples that follow are excerpts from the timing report generated from an Kintex UltraScale device implementation of the system-level example design. The purpose of the example is to illustrate where to find the required information. If the information is not easily located in the report, increase the maximum number of paths reported.

Locate Tqfpga by searching the timing report for flip-flop to pad path analysis at Max at Slow Process Corner, where the destination is identified as spi_c .

  • Tqfpga = I/O Datapath Delay (spi_c )
  • Tqfpga = 1.856 ns, maximum
Slack (MET): 15.037ns (required time - arrival time)
 Source: example_support_wrapper/example_support/example_spi/example_spi_byte/spi_c_ofd/C
 (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.556ns period=11.111ns})
 Destination: spi_c
 (output port clocked by clk {rise@0.000ns fall@5.556ns period=11.111ns})
 Path Group: clk
 Path Type: Max at Slow Process Corner
 Requirement: 11.111ns (clk rise@11.111ns - clk rise@0.000ns)
 Data Path Delay: 1.856ns (logic 1.476ns (79.523%) route 0.380ns (20.477%))
 Logic Levels: 1 (OBUF=1)
 Output Delay: -11.111ns
 Clock Path Skew: -5.294ns (DCD - SCD + CPR)
 Destination Clock Delay (DCD): 0.000ns = ( 11.111 - 11.111 )
 Source Clock Delay (SCD): 5.294ns
 Clock Pessimism Removal (CPR): 0.000ns
 Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
 Total System Jitter (TSJ): 0.071ns
 Total Input Jitter (TIJ): 0.000ns
 Discrete Jitter (DJ): 0.000ns
 Phase Error (PE): 0.000ns
 Clock Net Delay (Source): 2.304ns (routing 0.335ns, distribution 1.969ns)
 Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
 ------------------------------------------------------------------- -------------------
 (clock clk rise edge) 0.000 0.000 r
 K20 0.000 0.000 r clk (IN)
 net (fo=0) 0.000 0.000 example_ibuf/I
 K20 r example_ibuf/INBUF_INST/PAD
 K20 INBUF (Prop_INBUF_HRIO_PAD_O)
 0.805 0.805 r example_ibuf/INBUF_INST/O
 net (fo=1, routed) 0.092 0.897 example_ibuf/OUT
 K20 r example_ibuf/IBUFCTRL_INST/I
 K20 IBUFCTRL (Prop_IBUFCTRL_HRIO_I_O)
 0.043 0.940 r example_ibuf/IBUFCTRL_INST/O
 net (fo=1, routed) 1.967 2.907 example_support_wrapper/clk
 BUFGCE_X1Y24 r example_support_wrapper/example_bufg/I
 BUFGCE_X1Y24 BUFGCE (Prop_BUFCE_BUFGCE_I_O)
 0.083 2.990 r example_support_wrapper/example_bufg/O
 X2Y1 (CLOCK_ROOT) net (fo=1742, routed) 2.304 5.294 example_support_wrapper/example_support/example_spi/example_spi_byte/clk
 BITSLICE_RX_TX_X0Y172
 FDRE r example_support_wrapper/example_support/example_spi/example_spi_byte/spi_c_ofd/C
 ------------------------------------------------------------------- -------------------
 BITSLICE_RX_TX_X0Y172
 FDRE (Prop_OUT_FF_BITSLICE_COMPONENT_RX_TX_C_Q)
 0.626 5.920 r example_support_wrapper/example_support/example_spi/example_spi_byte/spi_c_ofd/Q
 net (fo=1, routed) 0.380 6.300 spi_c_OBUF
 AC23 r spi_c_OBUF_inst/I
 AC23 OBUF (Prop_OUTBUF_HPIOB_I_O)
 0.850 7.150 r spi_c_OBUF_inst/O
 net (fo=0) 0.000 7.150 spi_c
 AC23 r spi_c (OUT)
 ------------------------------------------------------------------- -------------------
 (clock clk rise edge) 11.111 11.111 r
 clock pessimism 0.000 11.111
 clock uncertainty -0.035 11.076
 output delay 11.111 22.187
 -------------------------------------------------------------------
 required time 22.187
 arrival time -7.150
 -------------------------------------------------------------------
 slack 15.037

Locate Tqfpga by searching the timing report for flip-flop to pad path analysis at Min at Fast Process Corner, where the destination is identified as spi_c .

  • Tqfpga = I/O Datapath Delay (spi_c )
  • Tqfpga = 0.919 ns, minimum
Slack (MET): 3.227ns (arrival time - required time)
 Source: example_support_wrapper/example_support/example_spi/example_spi_byte/spi_c_ofd/C
 (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.556ns period=11.111ns})
 Destination: spi_c
 (output port clocked by clk {rise@0.000ns fall@5.556ns period=11.111ns})
 Path Group: clk
 Path Type: Min at Fast Process Corner
 Requirement: 0.000ns (clk rise@0.000ns - clk rise@0.000ns)
 Data Path Delay: 0.919ns (logic 0.752ns (81.829%) route 0.167ns (18.171%))
 Logic Levels: 1 (OBUF=1)
 Output Delay: 0.000ns
 Clock Path Skew: -2.308ns (DCD - SCD - CPR)
 Destination Clock Delay (DCD): 0.000ns
 Source Clock Delay (SCD): 2.308ns
 Clock Pessimism Removal (CPR): -0.000ns
 Clock Net Delay (Source): 1.077ns (routing 0.127ns, distribution 0.950ns)
 Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
 ------------------------------------------------------------------- -------------------
 (clock clk rise edge) 0.000 0.000 r
 K20 0.000 0.000 r clk (IN)
 net (fo=0) 0.000 0.000 example_ibuf/I
 K20 r example_ibuf/INBUF_INST/PAD
 K20 INBUF (Prop_INBUF_HRIO_PAD_O)
 0.418 0.418 r example_ibuf/INBUF_INST/O
 net (fo=1, routed) 0.025 0.443 example_ibuf/OUT
 K20 r example_ibuf/IBUFCTRL_INST/I
 K20 IBUFCTRL (Prop_IBUFCTRL_HRIO_I_O)
 0.015 0.458 r example_ibuf/IBUFCTRL_INST/O
 net (fo=1, routed) 0.746 1.204 example_support_wrapper/clk
 BUFGCE_X1Y24 r example_support_wrapper/example_bufg/I
 BUFGCE_X1Y24 BUFGCE (Prop_BUFCE_BUFGCE_I_O)
 0.027 1.231 r example_support_wrapper/example_bufg/O
 X2Y1 (CLOCK_ROOT) net (fo=1742, routed) 1.077 2.308 example_support_wrapper/example_support/example_spi/example_spi_byte/clk
 BITSLICE_RX_TX_X0Y172
 FDRE r example_support_wrapper/example_support/example_spi/example_spi_byte/spi_c_ofd/C
 ------------------------------------------------------------------- -------------------
 BITSLICE_RX_TX_X0Y172
 FDRE (Prop_OUT_FF_BITSLICE_COMPONENT_RX_TX_C_Q)
 0.268 2.576 r example_support_wrapper/example_support/example_spi/example_spi_byte/spi_c_ofd/Q
 net (fo=1, routed) 0.167 2.743 spi_c_OBUF
 AC23 r spi_c_OBUF_inst/I
 AC23 OBUF (Prop_OUTBUF_HPIOB_I_O)
 0.484 3.227 r spi_c_OBUF_inst/O
 net (fo=0) 0.000 3.227 spi_c
 AC23 r spi_c (OUT)
 ------------------------------------------------------------------- -------------------
 (clock clk rise edge) 0.000 0.000 r
 clock pessimism 0.000 0.000
 output delay -0.000 0.000
 -------------------------------------------------------------------
 required time -0.000
 arrival time 3.227
 -------------------------------------------------------------------
 slack 3.227

Locate Tsfpga by searching the timing report for pad to flip-flop path analysis at Setup (Max at Fast Process Corner), where the source pad is identified as spi_q .

  • Tsfpga = I/O Datapath Delay (spi_q )
  • Tsfpga = 0.658 ns, maximum
Slack (MET): 23.825ns (required time - arrival time)
 Source: spi_q
 (input port clocked by clk {rise@0.000ns fall@5.556ns period=11.111ns})
 Destination: example_support_wrapper/example_support/example_spi/example_spi_byte/spi_q_ifd/D
 (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.556ns period=11.111ns})
 Path Group: clk
 Path Type: Setup (Max at Fast Process Corner)
 Requirement: 11.111ns (clk rise@11.111ns - clk rise@0.000ns)
 Data Path Delay: 0.658ns (logic 0.495ns (75.210%) route 0.163ns (24.790%))
 Logic Levels: 2 (IBUFCTRL=1 INBUF=1)
 Input Delay: -11.111ns
 Clock Path Skew: 2.318ns (DCD - SCD + CPR)
 Destination Clock Delay (DCD): 2.318ns = ( 13.429 - 11.111 )
 Source Clock Delay (SCD): 0.000ns
 Clock Pessimism Removal (CPR): 0.000ns
 Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
 Total System Jitter (TSJ): 0.071ns
 Total Input Jitter (TIJ): 0.000ns
 Discrete Jitter (DJ): 0.000ns
 Phase Error (PE): 0.000ns
 Clock Net Delay (Destination): 1.087ns (routing 0.127ns, distribution 0.960ns)
 Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
 ------------------------------------------------------------------- -------------------
 (clock clk rise edge) 0.000 0.000 r
 input delay -11.111 -11.111
 U21 0.000 -11.111 r spi_q (IN)
 net (fo=0) 0.000 -11.111 spi_q_IBUF_inst/I
 U21 r spi_q_IBUF_inst/INBUF_INST/PAD
 U21 INBUF (Prop_INBUF_HPIOB_PAD_O)
 0.495 -10.616 r spi_q_IBUF_inst/INBUF_INST/O
 net (fo=1, routed) 0.047 -10.569 spi_q_IBUF_inst/OUT
 U21 r spi_q_IBUF_inst/IBUFCTRL_INST/I
 U21 IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
 0.000 -10.569 r spi_q_IBUF_inst/IBUFCTRL_INST/O
 net (fo=1, routed) 0.116 -10.453 example_support_wrapper/example_support/example_spi/example_spi_byte/spi_q
 BITSLICE_RX_TX_X0Y186
 FDRE r example_support_wrapper/example_support/example_spi/example_spi_byte/spi_q_ifd/D
 ------------------------------------------------------------------- -------------------
 (clock clk rise edge) 11.111 11.111 r
 K20 0.000 11.111 r clk (IN)
 net (fo=0) 0.000 11.111 example_ibuf/I
 K20 INBUF r example_ibuf/INBUF_INST/PAD
 K20 INBUF (Prop_INBUF_HRIO_PAD_O)
 0.418 11.529 r example_ibuf/INBUF_INST/O
 net (fo=1, routed) 0.025 11.554 example_ibuf/OUT
 K20 IBUFCTRL r example_ibuf/IBUFCTRL_INST/I
 K20 IBUFCTRL (Prop_IBUFCTRL_HRIO_I_O)
 0.015 11.569 r example_ibuf/IBUFCTRL_INST/O
 net (fo=1, routed) 0.746 12.315 example_support_wrapper/clk
 BUFGCE_X1Y24 BUFGCE r example_support_wrapper/example_bufg/I
 BUFGCE_X1Y24 BUFGCE (Prop_BUFCE_BUFGCE_I_O)
 0.027 12.342 r example_support_wrapper/example_bufg/O
 X2Y1 (CLOCK_ROOT) net (fo=1742, routed) 1.087 13.429 example_support_wrapper/example_support/example_spi/example_spi_byte/clk
 BITSLICE_RX_TX_X0Y186
 FDRE r example_support_wrapper/example_support/example_spi/example_spi_byte/spi_q_ifd/C
 clock pessimism 0.000 13.429
 clock uncertainty -0.035 13.394
 BITSLICE_RX_TX_X0Y186
 FDRE (Setup_IN_FF_BITSLICE_COMPONENT_RX_TX_C_D)
 -0.022 13.372 example_support_wrapper/example_support/example_spi/example_spi_byte/spi_q_ifd
 -------------------------------------------------------------------
 required time 13.372
 arrival time 10.453
 -------------------------------------------------------------------
 slack 23.825

Locate Thfpga by searching the timing report for pad to flip-flop path analysis at Hold (Min at Slow Process Corner), where the source pad is identified as spi_q .

  • Thfpga = I/O Datapath Delay (spi_q )
  • Thfpga = 0.468 ns, minimum
Slack (MET): 17.334ns (arrival time - required time)
 Source: spi_q
 (input port clocked by clk {rise@0.000ns fall@5.556ns period=11.111ns})
 Destination: example_support_wrapper/example_support/example_spi/example_spi_byte/spi_q_ifd/D
 (rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@5.556ns period=11.111ns})
 Path Group: clk
 Path Type: Hold (Min at Slow Process Corner)
 Requirement: 0.000ns (clk rise@0.000ns - clk rise@0.000ns)
 Data Path Delay: 0.468ns (logic 0.242ns (51.750%) route 0.226ns (48.250%))
 Logic Levels: 2 (IBUFCTRL=1 INBUF=1)
 Input Delay: 22.222ns
 Clock Path Skew: 5.302ns (DCD - SCD - CPR)
 Destination Clock Delay (DCD): 5.302ns
 Source Clock Delay (SCD): 0.000ns
 Clock Pessimism Removal (CPR): -0.000ns
 Clock Net Delay (Destination): 2.312ns (routing 0.335ns, distribution 1.977ns)
 Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
 ------------------------------------------------------------------- -------------------
 (clock clk rise edge) 0.000 0.000 r
 input delay 22.222 22.222
 U21 0.000 22.222 r spi_q (IN)
 net (fo=0) 0.000 22.222 spi_q_IBUF_inst/I
 U21 r spi_q_IBUF_inst/INBUF_INST/PAD
 U21 INBUF (Prop_INBUF_HPIOB_PAD_O)
 0.242 22.464 r spi_q_IBUF_inst/INBUF_INST/O
 net (fo=1, routed) 0.050 22.514 spi_q_IBUF_inst/OUT
 U21 r spi_q_IBUF_inst/IBUFCTRL_INST/I
 U21 IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
 0.000 22.514 r spi_q_IBUF_inst/IBUFCTRL_INST/O
 net (fo=1, routed) 0.176 22.690 example_support_wrapper/example_support/example_spi/example_spi_byte/spi_q
 BITSLICE_RX_TX_X0Y186
 FDRE r example_support_wrapper/example_support/example_spi/example_spi_byte/spi_q_ifd/D
 ------------------------------------------------------------------- -------------------
 (clock clk rise edge) 0.000 0.000 r
 K20 0.000 0.000 r clk (IN)
 net (fo=0) 0.000 0.000 example_ibuf/I
 K20 INBUF r example_ibuf/INBUF_INST/PAD
 K20 INBUF (Prop_INBUF_HRIO_PAD_O)
 0.805 0.805 r example_ibuf/INBUF_INST/O
 net (fo=1, routed) 0.092 0.897 example_ibuf/OUT
 K20 IBUFCTRL r example_ibuf/IBUFCTRL_INST/I
 K20 IBUFCTRL (Prop_IBUFCTRL_HRIO_I_O)
 0.043 0.940 r example_ibuf/IBUFCTRL_INST/O
 net (fo=1, routed) 1.967 2.907 example_support_wrapper/clk
 BUFGCE_X1Y24 BUFGCE r example_support_wrapper/example_bufg/I
 BUFGCE_X1Y24 BUFGCE (Prop_BUFCE_BUFGCE_I_O)
 0.083 2.990 r example_support_wrapper/example_bufg/O
 X2Y1 (CLOCK_ROOT) net (fo=1742, routed) 2.312 5.302 example_support_wrapper/example_support/example_spi/example_spi_byte/clk
 BITSLICE_RX_TX_X0Y186
 FDRE r example_support_wrapper/example_support/example_spi/example_spi_byte/spi_q_ifd/C
 clock pessimism 0.000 5.302
 BITSLICE_RX_TX_X0Y186
 FDRE (Hold_IN_FF_BITSLICE_COMPONENT_RX_TX_C_D)
 0.054 5.356 example_support_wrapper/example_support/example_spi/example_spi_byte/spi_q_ifd
 -------------------------------------------------------------------
 required time -5.356
 arrival time 22.690
 -------------------------------------------------------------------
 slack 17.334

Check:

  • Is Thfpga ? Tqfpga,min + Tclqx ?
  • Is 0.468 ns ? 0.919 ns + 1 ns?
  • Is 0.468 ns ? 1.919 ns? Yes

Calculate:

Tclk ? 0.5 × (Tqfpga,max + Tw1 + Tdly + Tw2 + Tclqv + Tw3 + Tdly + Tw4 + Tsfpga )

requires

Tclk ? 0.5 × (1.856 ns + 1 ns + 2.8 ns + 1 ns + 6 ns + 1 ns + 2.8 ns + 1 ns + 0.658 ns)

or

Tclk ? 9.057 ns

The hold requirement is satisfied and the requirement on Tclk indicates that the SPI Receive Waveform and Timing Budget restrict the system-level design example input clock cycle time to be 9.057 ns or larger.