IP Design Checklist - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

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3.1 English

The following checklist is provided with the SEM controller to assist your use and integration of the IP.

Review the unsupported features (see Unsupported Features) when using the SEM IP to ensure compatibility with the design.

Decide on your SEU mitigation approach and make trade-offs of different features available in the IP. See Key Considerations for SEM IP Adoption.

Most would use the SEM controller in the Mitigation and Testing mode and in its default configuration as it enables SEU event detection and correction with the ability to inject errors, and has access to all the other convenience features in the Idle state. Others might opt to migrate to the Mitigation only mode during production to disable any error injection capabilities.

Consider if your system would take different actions if the IP reports a correctable error, uncorrectable error, correctable error that is essential, etc. For example, if a correctable error that is not essential is detected, do nothing but if a correctable error that is essential is detected, reconfigure the device. At the minimum, you should log all errors that are detected using the Monitor or UART interface.
Calculate a reliability estimation of a design (including SEM IP) using the pre-design (spreadsheet-based) SEU FIT estimation tool for your entire deployment to understand how frequently you can expect to log an error. The pre-design (spreadsheet-based) SEU FIT estimation tool can be downloaded from here: AMD Quality and Reliability Web Page
Verify that the system clock provided to the controller follows the recommended guidelines. See System Clock Interface. The SEM controller expects the clock provided to it and the configuration primitives to be stable (no glitching and does not violate FMax ). If the initial clock is unstable, employ the use of a BUFGCE to buffer the clock and only enable the buffer when the clock is stable.
Consider setting initial cap_gnt input to 0 and adding a master control switch on the signal to control when the controller initializes. cap_gnt should only be set to 1 when ICAP is ready.
Consider adding a master control switch on the clock provided to the controller. This determines when the clock is stable and provides it to the controller.
Check that all unused input ports are tied off as described in the individual sections of the Interface, see Interfaces. If the ports are not tied off correctly, the IP might not initialize.
Review all the system-level considerations for each used interface as described in the individual sections of Interface, see Interfaces.
For future debugging purposes, at the minimum AMD recommends buffering the Monitor Interface output into a FIFO. This information is required to debug any future issues. See Monitor Interface.
For future debugging purposes, AMD recommends that the post-synthesis DCP of the design is stored to debug any future issues.
When logging errors and location of the errored frame, use the Monitor or UART interface. See Monitor Interface and UART Interface. AMD discourages monitoring the FRAME_ECC interface.
If you are having issues with the UART interface (message is garbled, characters are being dropped, etc), check your V_ENABLETIME value settings are compatible to the baud rate and clock frequency that you selected. Also, that the external device or terminal emulator that the UART interface is connected to is configured correctly. See Switching Behavior.
Each SEM controller generated is specific to the device it is targeted for. Do not take a SEM controller generated for one device and use it for another device.

Check that the controller is correctly constrained as described in Constraining the Core.

  • Clock period constraints for the controller icap_clk
  • False path constraint on some asynchronous path between the controller and ICAP
  • ICAP and FRAME_ECC constraints might need to be applied for successful placement
It is not possible to observe controller behaviors in simulation but design simulations that instantiate the controller is supported. See Simulation.
Do not place any pipeline registers between the controller and the FRAME_ECC/ICAP primitives outside what is delivered in the example design.
Review Systems to consider if a system-level supervisory function is needed to monitor the Soft Error Mitigation solution.
Consider using block RAM ECC to protect your block RAMs from SEUs and other methods to further increase the design resiliency to soft errors if the estimated FIT of the design is not within the intended budget.
Integrate the SEM IP into your design cycle early and validate your design in hardware with it enabled. See Integration and Validation.
When debugging issues, see Debugging for further guidance.
For quick reference of how the IP should behave, see Figure 1 through Figure 3 that describe the valid state transition diagrams of the controller.
When performing error injection, execute a Query command before and after to verify the effects of the error injection. See Error Injection Guidance.